middle-end/6180: Infinite loop in cc1 during dbr pass

[David S. Miller]

   From: law@redhat.com
   Date: Tue, 04 Jun 2002 14:46:53 -0600

    > This could also, for example, make it much more easier to teach the
    > generic instruction scheduler how to do delay slotting so we can
    > obliterate reorg.

   Oh man.  Zapping reorg is conceptually simple if you look at it from
   the right angle (ie dependency graphs).  It'd also be a hell of a lot
   faster.
   
Pre-delay slots fall right out of that too :-)