Vector modes under hppa64-hpu

[Aldy Hernandez]

On Thu, Jul 25, 2002 at 09:49:55PM +0100, Joern Rennecke wrote:
>   	  else
>   	    t = simplify_gen_subreg (submode, target, mode, i * subsize);
> ! 	  if (CONSTANT_P (op0) || GET_CODE (op0) == REG)
>   	    a = simplify_gen_subreg (submode, op0, mode, i * subsize);
>   	  else
>   	    a = extract_bit_field (op0, subbitsize, i * subbitsize, unsignedp,
>   				   NULL_RTX, submode, submode, size);
> ! 	  if (CONSTANT_P (op1) || GET_CODE (op1) == REG)
>   	    b = simplify_gen_subreg (submode, op1, mode, i * subsize);
>   	  else
>   	    b = extract_bit_field (op1, subbitsize, i * subbitsize, unsignedp,
> 
> 
> That doesn't work when submode is smaller than a word.  At register allocation
> time, every subreg of a single hard register is assumed to be a low part,
> even if its not.

Can you take a look at his failure then?  It's preproducible with a
cross compiler, you just need to build cc1 on:

hppa1.0-hp-hpux11.00

aldy