GCC/powerpc AltiVec expectations.

[Kumar Gala]

Depending on how your context switching code is handling AltiVec 
registers the use of VRSAVE for a SVR4 ABI does not gain much.  Through 
lazy context switching its easier to save and restore all the vector 
registers then to test every bit position of VRSAVE to determine which 
registers to save or restore.

It also depends on what gcc actually puts into the VRSAVE register on 
entry and exit of a function which uses AltiVec.  I do not think the 
AltiVec PIM defines what should be placed in VRSAVE.  Does the gcc docs 
cover this?

- kumar


On Monday, July 1, 2002, at 04:56 PM, Matt Thomas wrote:

> At 02:35 PM 7/1/2002, Geoff Keating wrote:
>> Matt Thomas <matt@3am-software.com> writes:
>>
>> > I'm finishing off AltiVec support for NetBSD/powerpc and I was
>> > wondering what gcc's requirements are for the host system.
>> >
>> > Does it expect VRSAVE to be per-process or system-wide?
>>
>> It will have to be per-process, otherwise you have a race condition
>> when it is set.
>
> I guessed as much.  Too bad a mtspr X,256 doesn't cause a VEC trap.
> Dealing with VRSAVE is non-trivial otherwise.
>
>> > Does it expect all vector registers to be save on a context-switch
>> > or only those specified in VRSAVE?  What about VSCR?
>>
>> Only those in VRSAVE, plus VSCR.  However, you might decide that you
>> have to save all of them to ensure process isolation, in which case
>> you don't need VRSAVE at all.  VRSAVE is most useful on a system where
>> all processes trust each other.
>
> I was planning to use VRSAVE to control which ones to be saved.  On
> loading VRSAVE would control which would be vxor'ed (bit not set) or
> loaded (bit set).
>
>
> -- Matt Thomas               Internet:   matt@3am-software.com
> 3am Software Foundry      WWW URL:    http://www.3am-
> software.com/bio/matt/
> Cupertino, CA             Disclaimer: I avow all knowledge of this 
> message