condition codes, haifa-sched and virtual-stack-vars

[Richard Earnshaw]

If most insns clobber the condition code register, then trying to 
represent it at all to the compiler isn't very helpful.  GCC relies on 
being able to generate some types of insn without going through the 
expanders (simple moves for instance), so you might end up with spurious 
aborts if your normal move/addition/subtraction patterns require a clobber.

You don't have to use the CC0 approach however, it is possible to create a 
description of a machine that has no condition code register at all, and 
conditional branches (about the only time that conditions are really 
needed within the compiler) can be represented as compare-and-branch 
instructions.  See the TARGET_THUMB instructions of the ARM machine 
description for an example.

R.