RTL generation patterns

[Richard Earnshaw]

> hello
> 
> The following line of code 
> l=1;
> when cross compiled with the arm cross compiler
> produces the following load store rtl instructions:
> 
> (insn 10 7 11 (set (reg:SI 32)
>         (const_int 1 [0x1])) -1 (nil)
>     (expr_list:REG_EQUAL (const_int 1 [0x1])
>         (nil)))
> 
> (insn 11 10 14 (set (mem/f:SI (plus:SI (reg:SI 28)
>                 (const_int -16 [0xfffffff0])) 0)
>         (reg:SI 32)) -1 (nil)
>     (nil))
> 
> These instructions are generated form the following
> define expand:
> 
> define_expand "movsi"
>   [(set (match_operand:SI 0 "general_operand" "")
>         (match_operand:SI 1 "general_operand" ""))]
>  .....
> 
> I fail to understand how the second rtl
> (store)instrucion is generated from this pattern. how
> does  
> (match_operand:SI 0 "general_operand" "") produce
> (mem/f:SI (plus:SI (reg:SI 28)
>                 (const_int -16 [0xfffffff0])) 0)
> shouldnt it only produce a single rtl instruction like
> only a mem? please comment 

This is a "define_expand" pattern, which executes the block of code in the 
body of the pattern to generate the RTL.  That code contains rules to 
handle cases that aren't legal instructions for the ARM: moving a constant 
directly to memory is one the the cases that is handled in this manner.

      /* Everything except mem = const or mem = mem can be done easily */
      if (GET_CODE (operands[0]) == MEM)
        operands[1] = force_reg (SImode, operands[1]);
      if (GET_CODE (operands[1]) == CONST_INT
          && !(const_ok_for_arm (INTVAL (operands[1]))
               || const_ok_for_arm (~INTVAL (operands[1]))))
        {


R.