SImode -> DImode optimizations

[Alan Modra]

What's the correct way to let gcc know that SImode insn patterns
leave the high part of a reg in a known state?  eg.  powerpc has

(define_insn "rotlsi3"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
		   (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
  ""
  "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")

On PowerPC64, this particular insn is guaranteed to leave the high
32 bits of the reg zero.  I'd like to avoid gcc generating
unnecessary zero_extendsidi2 insns.  I know this can be done by
writing appropriate patterns that combine both operations and emit
a single rlwinm machine insn, but that leaves the zero_extend in
the rtl.  What I'm after is a way of zapping the zero_extend, so
that eg.

 rotlsi3
 zero_extendsidi2
 cmpsi 0

is optimized into one insn in the same way as is done for

 rotlsi3
 cmpsi 0

Or do I have to write a bunch of 3 insn combiners?

Hmm, or something different, like specifying the output of rotlsi3
and other similar instructions is really DImode?  If so, how to
do this without breaking things horribly?

-- 
Alan Modra
IBM OzLabs - Linux Technology Centre