An unusual Performance approach using Synthetic registers, and a request for guidance.

[Dave Hudson]

Hi Paolo,

Bonzini wrote:
> That's not unusual.  If one had, say, to write a back-end for the 6502, one
> might think of representing the zero-page as caller-save registers, and hide
> the weeny three registers A,X,Y from the middle-end (using them only
> internally, or very near to this).  I also hope that because of the good L1
> coherency of the stack, this might pay well on the x86 as well.  The only
> problem might be in the lack of orthogonality in the x86 instruction set.

This strategy is exactly what the IP2k port of gcc does.  We use 32 
directly addressable memory locations as our common "registers" and 
expose the two pointer and stack pointer regs.  We completely hide the 
accumulator register W and the partial multiply result MULH.  All of our 
normal insn patterns start off not understanding anything about the 
hidden regs and then in the machine-dependent reorg we split insn 
patterns into ones that explicitly use the previously hidden regs and 
run a series of processor-specific passes to eliminate any redundancy.

It's not pretty, but it does work very well.


Regards,
Dave