a regression on 2.95.3 (was Re: How can I submit a large testresult?)

[Kazu Hirata]

Hi Bernd,

> > Looking at the difference between the above testresult, there are at
> > least two regression, one of which I have a patch for.
>
> Argh.  Do you know what caused them?

Yes.  Here is what happens with 20000313-1.c.  Loading -1 into a
register in SImode does not set cc0 appripriately, but it is
machine-described as it does.  The insn does the job by first
subtracting the register from itself and then decrement it by 1.  The
decrement part does not set cc0, so the cc0 of the insn must be
"clobber".

The attached patch addresses the problem by saying that loading of an
integer (other than 0) clobbers cc0.  The first hunk of the patch
splits the alternative No. 2 into two alternatives, integer loading
and mem-to-reg move.  The second hunk pushes alternative numbers 6, 7,
8 to 7, 8, 9 due to the split.  The last hunk accordingly splits the
alternative No. 2 into two pieces.

Another problem is that fixing this causes other regressions in
execution tests even though the patch is so obvious; gcc merely
inserts test instructions due to "clobber" if cc0 is needed for a
conditional branch.  I'll try to resolve this over the weekend, but
please don't consider this a showstopper as it is expected to take
some time to fix the chaining problems.  I hate to dishonor "no
regression" status, but I do appreciate that gcc-2.95.3 addresses so
many failures!

p.s.
It feels weired that CSE leaves code like "constant loading followed
by a conditional branch based on the constant" when -finline-functions
is specified.

Thanks,

Kazu Hirata

*** h8300.md.org	Thu Feb 22 03:44:32 2001
--- h8300.md	Thu Feb 22 03:46:04 2001
***************
*** 401,408 ****
     (set_attr "cc" "clobber")])
  
  (define_insn "movsi_h8300hs"
!   [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,m,<,r,*a,*a,r")
! 	(match_operand:SI 1 "general_operand_src" "I,r,im,r,r,>,I,r,*a"))]
    "(TARGET_H8300S || TARGET_H8300H)
     && (register_operand (operands[0], SImode)
         || register_operand (operands[1], SImode))"
--- 401,408 ----
     (set_attr "cc" "clobber")])
  
  (define_insn "movsi_h8300hs"
!   [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,r,m,<,r,*a,*a,r")
! 	(match_operand:SI 1 "general_operand_src" "I,r,i,m,r,r,>,I,r,*a"))]
    "(TARGET_H8300S || TARGET_H8300H)
     && (register_operand (operands[0], SImode)
         || register_operand (operands[1], SImode))"
***************
*** 410,420 ****
  {
    if (which_alternative == 0)
      return \"sub.l	%S0,%S0\";
-   if (which_alternative == 6)
-     return \"clrmac\";
    if (which_alternative == 7)
!     return \"clrmac\;ldmac %1,macl\";
    if (which_alternative == 8)
      return \"stmac	macl,%0\";
    if (GET_CODE (operands[1]) == CONST_INT)
      {
--- 410,420 ----
  {
    if (which_alternative == 0)
      return \"sub.l	%S0,%S0\";
    if (which_alternative == 7)
!     return \"clrmac\";
    if (which_alternative == 8)
+     return \"clrmac\;ldmac %1,macl\";
+   if (which_alternative == 9)
      return \"stmac	macl,%0\";
    if (GET_CODE (operands[1]) == CONST_INT)
      {
***************
*** 444,451 ****
      }
     return \"mov.l	%S1,%S0\";
  }"
!   [(set_attr "length" "2,2,10,10,4,4,2,6,4")
!    (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
  
  (define_insn "movsf_h8300h"
    [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
--- 444,451 ----
      }
     return \"mov.l	%S1,%S0\";
  }"
!   [(set_attr "length" "2,2,10,10,10,4,4,2,6,4")
!    (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
  
  (define_insn "movsf_h8300h"
    [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")