WORD_REGISTER_OPERATIONS/LOAD_EXTEND_OP

[Richard Earnshaw]

> Can someone tell me what assumptions are made by this piece of code in
> combine.c (nonzero_bits):

IIRC they are:

(REG:mode1 x) has just been loaded from memory.

mode1 < word size (mode2)

loads of size mode1 zero- or sign-extend automatically to mode2.  That is, 
in effect

(set (reg:mode1 x) (mem:mode1 ...))

is equivalent to

(set (reg:mode1 x) (subreg:mode1 (..._extend:mode2 (mem:mode1 ...)) 0))

for this machine.

> 
> #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
>           /* If this is a typical RISC machine, we only have to worry
>              about the way loads are extended.  */
>           if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
>               ? (((nonzero
>                    & (((unsigned HOST_WIDE_INT) 1
>                        << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
>                   != 0))
>               : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
> #endif
> 
> I've got a sparc testcase here (PR 1061) where a masking operation is missing
> in the output.  It appears that this piece of code assumes that if W_R_O and
> L_E_O are defined, an expression like (subreg:SI (reg:HI x)) always has all
> bits zero in the upper half.  This isn't the case, though - this seems like
> it's just an invalid optimization and should be removed.
> 
> Comments?
> 
> 
> Bernd
>