GCC build failed with your patch on 2000-09-29T11:50:00Z.

[Geoff Keating]

Jan Hubicka <jh@suse.cz> writes:

> > Now, I can fix these.  I am preparing a patch to fix some of them
> > (hopefully enough to be able to build again) now.  However, not all of
> > them would have been caught by the abort().  So I'm also going to send
> > in a patch that improves the abort() so that it scans through all of
> > the insn, and generates a warning instead.  This way we can determine
> > how bad the situation is.
> Thanks. I am almost convienced myself that requiring this order is not good
> idea, but I am really curious what your conclusion will be.
> The speedups are tiny overall, but perhaps we can bring more once more parts
> of compiler know about this rule.
> Most of the gain is due to reduced amount of find_reg_note calls - originally
> it just called it for each parallel, but now I am doing the call only for
> parallel with multiple sets, this can be archieved even w/o this new rule.
> 
> Please keep me updated about the process.

I've looked into it further and I think it can't be done.

The problem is this pattern:

(define_insn ""
  [(match_parallel 0 "store_multiple_operation"
		   [(set (match_operand:SI 1 "indirect_operand" "=Q")
			 (match_operand:SI 2 "gpc_reg_operand" "r"))
		    (clobber (match_scratch:SI 3 "=q"))])]
  "TARGET_STRING && TARGET_POWER"
  "{stsi|stswi} %2,%P1,%O0"
  [(set_attr "type" "store")])

How do I tell reload that the scratch register must match the 'q'
constraint?  It has to be an operand, and there's no way in a
match_parallel to specify an operand after the first part of the
PARALLEL.

The full insns look like

(insn 4 250 6 (parallel[ 
            (set (mem:SI (reg:SI 122) 6)
                (reg:SI 3 r3))
            (clobber (scratch:SI))
            (set (mem:SI (plus:SI (reg:SI 122)
                        (const_int 4 [0x4])) 6)
                (reg:SI 4 r4))
            (set (mem:SI (plus:SI (reg:SI 122)
                        (const_int 8 [0x8])) 6)
                (reg:SI 5 r5))
            (set (mem:SI (plus:SI (reg:SI 122)
                        (const_int 12 [0xc])) 6)
                (reg:SI 6 r6))
            (set (mem:SI (plus:SI (reg:SI 122)
                        (const_int 16 [0x10])) 6)
                (reg:SI 7 r7))
            (set (mem:SI (plus:SI (reg:SI 122)
                        (const_int 20 [0x14])) 6)
                (reg:SI 8 r8))
            (set (mem:SI (plus:SI (reg:SI 122)
                        (const_int 24 [0x18])) 6)
                (reg:SI 9 r9))
            (set (mem:SI (plus:SI (reg:SI 122)
                        (const_int 28 [0x1c])) 6)
                (reg:SI 10 r10))
        ] ) 301 {*movti_ppc64+2} (nil)
    (nil))

-- 
- Geoffrey Keating <geoffk@cygnus.com>