Need advice on interface to non-gcc scheduler

[Damjan Lampret]

Hi Steven,

is your architecture similar to something like
http://www.opencores.org/cores/or2k/ ? I've tried to model OpenRISC 2000 in
GCC but GCC doesn't understand very good concept of distributed register
file. I've tried this with register classes defining a new register class
for each functional unit and its registers. Of course since GCC was designed
for traditional CPUs where you have one central register file it does not
generate efficient code for CPU similar to OR2K. I would be interested if
anyone has better idea how to model OR2K in GCC so that GCC would generate
efficient code?

regards, Damjan

----- Original Message -----
From: Steven Roos <S.Roos@its.tudelft.nl>
To: <gcc@gcc.gnu.org>
Sent: Friday, March 31, 2000 12:58 PM
Subject: Need advice on interface to non-gcc scheduler


> Hi,
>
> Currently I am working on an instruction scheduler for a new computer
> architecture. This new architecture is not like any current
> architecture and I guess there is no way to make gcc generate code
> for it.
>
> The architecture looks like an extremely wide VLIW with limited
> connectivity. To avoid long wires wherever possible, all resources
> are distributed over all units. The concept of a centralized register
> file does not exist. When scheduling an instruction all related data
> transports have to be scheduled explicitly too.
>
> My idea is to use as much of gcc as possible and send the gcc RTL code
> to a dedicated scheduler just before gcc would do its own scheduling.
>
> I would like some advice on how to implement this interface. How hard is
> it to generate such an interface? Can I get all sorts of analysis info
> (mem alias, data flow, control flow) through this interface? How about
> profiling info and debug info?
>
> Greetings,
> Steven Roos
> Delft University of Technology
>