UltraSPARC code generation weirdness

[David S. Miller]

   Date: Mon, 6 Mar 2000 14:15:52 -0800
   From: Aaron Holtzman <aholtzma@ess4.engr.UVic.CA>

   Am I doing something silly or does gcc just not support generating
   hardware multiplies that are supposedly in Sparc V7 and up?

Nothing is wrong, the compiler knows the timing characteristics
of the hardware multiply instruction on UltraSparc and knows
that the synthesized "shift/add" expansion will always execute
faster in your example.

It will emit the hardware multiply, but only in situations where
the compiler believes that the "shift/add" expansion will be
more expensive in cycles than the hardware multiply.

Later,
David S. Miller
davem@redhat.com