Porting GCC: Compare-and-Branch-Instructions

Anja Müller Mueller-Lehnitz@t-online.de
Fri Feb 4 08:46:00 GMT 2000

referring to my project of porting the GCC for the Intel
8051 microcontroler I have some questions about the handling of Conditional
Branch Instructions. Usually the GCC generates a pair of consecutive RTL
insns to produce conditional branches. The first insn is for the Comparison
and to set the Condition Code Status, the second one performs the Conditional
Branch depending on the Condition Code Status -> i.e. "Branch if lower
than" = "cmphi" + "blt".
The 8051 microcontroler has an opcode for Conditional
Branches -> CJNE. This Instruction compares two Operands and jumps if the
two Operands are not equal. Furthermore the Carry-Flag is set, when the
first Operand is lower than the second one. Besides there are some other
Opcode that work in a similar way. So I assume, that it is not necessary
to split up the Conditional Branch into two instructions. To solve this
problem I found the following passage in the GCC-Documentation "Using and
porting the GCC" :
"Some machines have compare-and-branch instructions
and no condition code. A similar technique works for them.
When it is time to "output" a compare instruction,
record its operands in two static variables. When outputting the
branch-on-condition-code instruction that follows,
actually output a compare-and-branch instruction that uses the
remembered operands.
It also works to define patterns for compare-and-branch
instructions. In optimizing compilation, the pair of compare
and branch instructions will be combined according
to these patterns. But this does not happen if optimization is not
requested. So you must use one of the solutions above
in addition to any special patterns you define. "
(Chapter: Machine Description -> Defining Jump Instruction
But how can I " record operands in static variables "
and how can I " use the remembered operands " in the Instruction Pattern
? Can you give me an example ? Here is my Instruction Pattern for the Comparison:
(define_insn "cmpqi"
  [(set (cc0) (compare
(match_operand:QI 0 "register_operand" "%a,a")
(match_operand:QI 1 "nonmemory_operand" "r,i")))]
What do have to write into the Output Template to record
the two operands ?
And here is i.e. the Instruction Pattern for the Equal-To-Comparison:
(define_insn "beq"
  [(set (pc)
(lt (cc0)
(const_int 0))
(label_ref (match_operand 0 "" ""))
What do have to write into the Output Template to get
the two operands from the other Instruction Pattern?
Or do you know another GCC Target Machine that works this
way so that I can read its machine description ?
Thank you !!!
Kind Regards

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