RFC: Prefetch instruction support

[Tim Prince]

Very interesting, and thanks for posting such a full explanation.  My
experience with prefetch and unrolling (on hppa and mips processors) would
indicate that it is not generally useful to increase the amount of unrolling
in order to increase prefetch distance, or, to put it the other way,
prefetch distance should not be made so large that more unrolling is used
than otherwise would be desirable.  Also, prefetch may not be desirable for
sequential (unit stride) access while it may be quite useful for larger
strides.  That depends on the application as well as the
processor.  It's not good to base the optimizations on simple benchmarks, if
the problems of real interest stress the cache size much more than the
benchmarks.


----- Original Message -----
From: "Frank Heldt" <Frank.Heldt@t-online.de>
To: "Jan Hubicka" <hubicka@atrey.karlin.mff.cuni.cz>
Cc: <egcs@egcs.cygnus.com>; <alex.dreyzen@amd.com>; <norbert.juffa@amd.com>
Sent: Tuesday, April 11, 2000 1:17 PM
Subject: Re: RFC: Prefetch instruction support


> Hello Jan,
>
> really nice work. I hope this will become part of gcc, it will be
> usefull not only on the Athlon (IIRC, the new Intel VTune Compiler makes
> massive use of prefetching on the PIII, which gives it a *big* boost).
>
> > During last weekend I've implemented basic prefetch instruction
framework
> > (tested on Athlon) based on the suggestions of Alex Dreyzen and Norbert
Juffa
> > from AMD.
> One question: Do the prefetch instructions only work on the Athlon?
> I remember vague, that the K6-II has them also (partly). It would be
> nice if the K6-II can use this feature too.
>
> Well done, Jan. Thanks alot.
>
> Frank
>
> --
> Frank Heldt
> mailto:Frank.Heldt@t-online.de
> mailto:Frank.Heldt@mahr.de
>