RFC: Prefetch instruction support

[norbert.juffa@amd.com]

Frank:

You are correct. PREFETCH and PREFETCHW were introduced as part of the
3DNow! instruction set with K6-2. Unfortunately, on a K6 platform its
almost impossible to get additional performance by using PREFETCH(W).
For one thing, memory throughput is limited by the Super7 bus. The
other major restriction is that K6-family CPUs allow only one outstanding
prefetch, which doesn't really get you anywhere unless a loop has lots
of computation and few loads.

The few situations where prefetch has some minor benefit on K6 are
spelled out in the 3DNow! porting guide.

For a compiler, it's not worth bothering trying to use PREFETCH(W) on
K6.


-- Norbert



> -----Original Message-----
> From: Frank.Heldt@t-online.de [ mailto:Frank.Heldt@t-online.de ]
> Sent: Tuesday, April 11, 2000 1:18 PM
> To: Jan Hubicka
> Cc: egcs@egcs.cygnus.com; Dreyzen, Alex; Juffa, Norbert
> Subject: Re: RFC: Prefetch instruction support
> 
> 
> Hello Jan,
> 
> really nice work. I hope this will become part of gcc, it will be
> usefull not only on the Athlon (IIRC, the new Intel VTune 
> Compiler makes
> massive use of prefetching on the PIII, which gives it a *big* boost).
> 
> > During last weekend I've implemented basic prefetch 
> instruction framework
> > (tested on Athlon) based on the suggestions of Alex Dreyzen 
> and Norbert Juffa
> > from AMD.
> One question: Do the prefetch instructions only work on the Athlon?
> I remember vague, that the K6-II has them also (partly). It would be
> nice if the K6-II can use this feature too.
> 
> Well done, Jan. Thanks alot.
> 
> 	Frank
> 
> -- 
> Frank Heldt
> mailto:Frank.Heldt@t-online.de
> mailto:Frank.Heldt@mahr.de
>