Fwd: Questions on PA machine description?
Jerry Quinn
jquinn@nortelnetworks.com
Mon Mar 8 06:49:00 GMT 1999
Oops - got the address wrong the first time
> From: "Jerry Quinn" <jquinn@nortelnetworks.com>
> To: egcs@egcs.cyngus.com
> Subject: Questions on PA machine description?
> Date: Fri, 5 Mar 1999 16:43:35 +0000
> X-Orig: <jquinn@americasm01.nt.com>
>
> Can someone help me understand function unit descriptions a bit better?
>
> I've been playing with machine function unit desriptions recently. Looking at
> the pa7100LC description for ALU, I'm a bit confused. The following is the
> description:
>
> ;; We have two basic ALUs.
> (define_function_unit "pa7100LCalu" 2 2
> (and
> (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,
> fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
> (eq_attr "cpu" "7100LC,7200")) 1 1)
>
> It says there are 2 ALU's. The READY=1 and DELAY=1 appear to me to be a gate
> so that each unit can be issued 1 insn per cycle. What is confusing is the
> SIMULTANEITY of 2. The documentation claims that this means that each unit
> can have two active insns issued at a time. But this isn't true. A total of
> two insns can be issued by using both units. Is the documentation wrong, the
> function unit description wrong, or is it a convenient means of accomplishing
> something I don't understand?
>
> Also, my reading of the definition of SIMULTANEITY seems to indicate that it
> should be 1 for the pa7100LCfp_div function unit since the div/sqrt portion of
> the FPU can only execute one insn at a time. Is this correct or wrong?
>
> Second question:
>
> There is a comment that shifts and memory ops execute in one of the ALU's but
> that that can't be modeled. Can someone explain what that means. What PA
> descriptions I've found so far (I haven't seen many) seem to say that shift
> and merge are ALU ops just like integer add so the comment doesn't seem
> justified, but it's there for a reason. Also, how do memory ops fit into
> this?
>
> Thanks
>
> - --
> Jerry Quinn Tel: (514) 761-8737
> jquinn@nortelnetworks.com Fax: (514) 761-8505
> Speech Recognition Research
>
To : "Quinn, Jerry (J.) [EXCHANGE:MTL:6X17:BNR]" <jquinn@americasm01.nt.com>
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From: "Jerry Quinn" <jquinn@nortelnetworks.com>
To: egcs@egcs.cyngus.com
Subject: Questions on PA machine description?
Date: Fri, 5 Mar 1999 16:43:35 +0000
X-Orig: <jquinn@americasm01.nt.com>
Can someone help me understand function unit descriptions a bit better?
I've been playing with machine function unit desriptions recently. Looking at
the pa7100LC description for ALU, I'm a bit confused. The following is the
description:
;; We have two basic ALUs.
(define_function_unit "pa7100LCalu" 2 2
(and
(eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,
fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
(eq_attr "cpu" "7100LC,7200")) 1 1)
It says there are 2 ALU's. The READY=1 and DELAY=1 appear to me to be a gate
so that each unit can be issued 1 insn per cycle. What is confusing is the
SIMULTANEITY of 2. The documentation claims that this means that each unit
can have two active insns issued at a time. But this isn't true. A total of
two insns can be issued by using both units. Is the documentation wrong, the
function unit description wrong, or is it a convenient means of accomplishing
something I don't understand?
Also, my reading of the definition of SIMULTANEITY seems to indicate that it
should be 1 for the pa7100LCfp_div function unit since the div/sqrt portion of
the FPU can only execute one insn at a time. Is this correct or wrong?
Second question:
There is a comment that shifts and memory ops execute in one of the ALU's but
that that can't be modeled. Can someone explain what that means. What PA
descriptions I've found so far (I haven't seen many) seem to say that shift
and merge are ALU ops just like integer add so the comment doesn't seem
justified, but it's there for a reason. Also, how do memory ops fit into
this?
Thanks
- --
Jerry Quinn Tel: (514) 761-8737
jquinn@nortelnetworks.com Fax: (514) 761-8505
Speech Recognition Research
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