gcc-2.95 and SGI STL 3.2

[Richard Henderson]

On Tue, Jun 22, 1999 at 12:39:01PM +0000, Dima Volodin wrote:
> >But as I understand it, these operations may not be available on all
> >systems, and if they are, may have different interfaces.
> 
> Besides, doing atomic operations is not enough for guaranteeing data
> consistency - it's a recurring topic on comp.programming.threads, you
> might want to check Dave Butenhof's articles there or just get his book
> and see the part about the memory model in POSIX threads.

There aren't that many variations that need to be delt with,
and the win speedwise is large enough it's worth the effort.

Just consider everything to use a relaxed memory order and
define macros that ensure ordering of a particular type
(load-load, load-store, store-load, store-store, and sync).
For systems that ensure one of those naturally, the macro
becomes an effective nop.

As for the different interfaces to the atomic operations, all of
the interesting extant processors support either atomic add (i386,
ia64), compare and exchange (m68k, i486, sparcv9, ia64) or load
locked store conditional (mips, alpha, ppc).  Again, not that
many variants to choose from.


r~