Question on parallel execution inside the processor

[Jeffrey A Law]

  In message < 199806231329.PAA27951@keksy.mchp.siemens.de >you write:
  > Hi,
  > is there any pass in egcs, which tries to schedule instructions
  > in a way, that no pipeline stalls occur any more?
The scheduler attempts to do this.

  > The haifa scheduler optimizes on RTL code - doesn't it?
Yes.

  > So it can't know anything about assembler instructions,
Nor does any other pass in the compiler.

  > which can only be executed in pipeline X and therefor 
  > shouldn't be preceeded by instructions which only
  > work in X, too. A good compiler would try to put
  > instructions in between.
GCC does this.  Basically each hunk of RTL has a series of attributes
which describe the type of operation it performs.

In the machine description we can map from instruction types to
pipeline units.  Thus the scheduler has the information it needs
to schedule instructions to avoid pipeline stalls.


jeff