patch: alpha haifa abort

[John Carr]

> 	I have been looking for ways to teach GCC to generate the PowerPC
> byte-swapping instructions (they are not present in the original POWER
> architecture which did not have a sense of little-endian ordering) for
> years.  Michael Tiemann and I discussed this many years ago, but GCC
> combine pass does not see enough RTL patterns at one time.

Recognizing shift-and-mask sequences would be helpful, but I don't
think it is essential.

I was thinking about adding a new builtin function and a new rtl code.
So, for example, one might have after macro expansion

	int x = __load_big_endian(ptr);

which became

	(set (reg x) (swap (mem (reg ptr))))


This would go through CSE as an atomic operation.  The alpha machine
description would have a define_split to allow scheduling of the
individual machine instructions.  SPARC and RS/6000 might not.


I am nearly certain that the original POWER did define byte swapping
load and store instructions even though it was big-endian only.