patch: alpha haifa abort

[Richard Henderson]

[ Ref http://www.cygnus.com/ml/egcs-bugs/0404.html for the test case. ]

The problem is with these two instructions:

(insn/i 123 64 66 (parallel[ 
            (set (reg/v:DI 17 $17)
                (asm_operands ("insbl  %3,3,%1         # %1 = dd000000
	zapnot %3,2,%2         # %2 = 0000cc00
	sll    %2,8,%2         # %2 = 00cc0000
	or     %2,%1,%1        # %1 = ddcc0000
	zapnot %3,4,%2         # %2 = 00bb0000
	extbl  %3,3,%0         # %0 = 000000aa
	srl    %2,8,%2         # %2 = 0000bb00") ("=r") 0[ 
                        (subreg:SI (reg:DI 0 $0) 0)
                    ] 
                    [ 
                        (asm_input:SI ("r"))
                    ]  ("../../../0404.c") 189))
            (set (reg/v:DI 3 $3)
                (asm_operands ("insbl  %3,3,%1         # %1 = dd000000
	zapnot %3,2,%2         # %2 = 0000cc00
	sll    %2,8,%2         # %2 = 00cc0000
	or     %2,%1,%1        # %1 = ddcc0000
	zapnot %3,4,%2         # %2 = 00bb0000
	extbl  %3,3,%0         # %0 = 000000aa
	srl    %2,8,%2         # %2 = 0000bb00") ("=&r") 1[ 
                        (subreg:SI (reg:DI 0 $0) 0)
                    ] 
                    [ 
                        (asm_input:SI ("r"))
                    ]  ("../../../0404.c") 189))
            (set (reg/v:DI 2 $2)
                (asm_operands ("insbl  %3,3,%1         # %1 = dd000000
	zapnot %3,2,%2         # %2 = 0000cc00
	sll    %2,8,%2         # %2 = 00cc0000
	or     %2,%1,%1        # %1 = ddcc0000
	zapnot %3,4,%2         # %2 = 00bb0000
	extbl  %3,3,%0         # %0 = 000000aa
	srl    %2,8,%2         # %2 = 0000bb00") ("=&r") 2[ 
                        (subreg:SI (reg:DI 0 $0) 0)
                    ] 
                    [ 
                        (asm_input:SI ("r"))
                    ]  ("../../../0404.c") 189))
        ] ) -1 (insn_list:REG_DEP_ANTI 50 (insn_list:REG_DEP_OUTPUT 62 (insn_list 119 (nil))))
    (expr_list:REG_DEAD (reg:DI 0 $0)
        (nil)))

(insn/i 124 138 132 (set (subreg:DI (reg:SI 17 $17) 0)
        (plus:DI (reg/v:DI 17 $17)
            (reg/v:DI 2 $2))) 7 {adddi3} (insn_list:REG_DEP_ANTI 50 (insn_list:REG_DEP_OUTPUT 62 (insn_list 123 (insn_list 123 (nil)))))
    (expr_list:REG_DEAD (reg/v:DI 17 $17)
        (expr_list:REG_DEAD (reg/v:DI 2 $2)
            (nil))))

Note the double dependance 124 has on 123.

As an asside, anyone know of a way I might be able to protect
asm blocks from interblock scheduling?  Not critical, but it
would happen to be better in this case.


r~