mips16/mips64 frame ptr to stack ptr

[Nigel Stephens]

> The following patch prevents the elimination of the frame pointer
> by the stack pointer when both TARGET_MIP16 and TARGET_64BIT.
> It is an overly pesimistic way to solve this problem, but my attempts
> to find a less pervasive solution have failed.  My suggestion
> is to install this patch, so that we at least get correct though
> less optimal code, while/until we have a more optimal solution.

This alternative patch is also not ideal, but at least restricts
itself to just fixing up the fairly rare use of lwu, and doesn't
produce worse code in the normal case.

________________________________________________________________________
Nigel Stephens, Algorithmics Ltd, 3 Drayton Park, London N5 1NU. England
mailto:nigel@algor.co.uk                          http://www.algor.co.uk
phone:+44 171 700 3301	   mobile:+44 976 686470    fax:+44 171 700 3400

	* config/mips/mips.c (mips_move_1_word): We can't do a simple 			"lwu" for unsigned loads in 64-bit mode with -mips16 if the 
	base register is the stack pointer, instead we have do do 
	a "lw" and manually zero-extend.

Index: mips.c
===================================================================
RCS file: /vol/cvsroot/gnu/egcs/gcc/config/mips/mips.c,v
retrieving revision 1.1.1.1.2.2
diff -p -c -r1.1.1.1.2.2 mips.c
*** mips.c	1997/12/19 13:14:17	1.1.1.1.2.2
--- mips.c	1998/02/21 17:43:22
*************** mips_move_1word (operands, insn, unsigne
*** 1729,1737 ****
  		  break;
  		case SImode:
  		case CCmode:
! 		  ret = ((unsignedp && TARGET_64BIT)
! 			 ? "lwu\t%0,%1"
! 			 : "lw\t%0,%1");
  		  break;
  		case HImode:
  		  ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
--- 1827,1850 ----
  		  break;
  		case SImode:
  		case CCmode:
! 		  if (unsignedp && TARGET_64BIT)
! 		    {
! 		      /* mips16 doesn't allow lwu directly off $sp, we
! 		         should catch this in REGNO_MODE_OK_FOR.., but
! 		         we don't know that it is unsigned there, so we
! 		         have to do this last minute kludge. This can
! 		         happen zero-extending one half of a computed
! 			 64-bit result. */
! 		      if (TARGET_MIPS16
! 			  && GET_CODE (XEXP (op1, 0)) == PLUS
! 			  && (GET_CODE (XEXP (XEXP (op1, 0), 0)) == REG
! 			      && REGNO (XEXP (XEXP (op1, 0), 0)) ==  STACK_POINTER_REGNUM))
! 			ret = "lw\t%0,%1\n\tdsll\t%0,32\n\tdsrl\t%0,32";
! 		      else
! 			ret = "lwu\t%0,%1";
! 		    }
! 		  else
! 		    ret = "lw\t%0,%1";
  		  break;
  		case HImode:
  		  ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";