alpha extendsidi2 bogisity [was: egcs on alpha...]

[Richard Henderson]

On Fri, Apr 03, 1998 at 06:54:06PM -0500, Cristian Gafton wrote:
> ./xgcc -B./  -DIN_GCC    -W -Wall -O2 -O2 -I./include  -I. -I../../gcc
> -I../../gcc/config \
> -c ../../gcc/objc/hash.c -o objc/hash.o
> xgcc: Internal compiler error: program cc1 got fatal signal 6

Yes, someone pointed this out to me the other night.  The problem is

Tue Jun  1 07:41:26 1993  Richard Kenner  (kenner@vlsi1.ultra.nyu.edu)

        * alpha.md (extendsidi2): Correctly do operation when in FP
        registers and, since expensive, don't have FP regs as a preference.

For some reason of register allocation, the third case of extendsidi2
never seemed to get triggered before.  But cvtql;cvtlq is _not_ a safe
operation on an existing 32-bit quantity.

The abort above is caused by this sequence being applied to the value 32,
rendering 0, which is then fed to a division.  SIGFPE is caught, and 
abort is thrown.

The simplest solution is the following.  I want to come up with something
better though, that at least allows the lds;cvtlq sequence.  But they've
got to be split, otherwise we stall hard...


r~



Index: alpha.md
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/alpha/alpha.md,v
retrieving revision 1.31
diff -c -p -d -r1.31 alpha.md
*** alpha.md	1998/03/31 19:20:08	1.31
--- alpha.md	1998/04/04 01:22:40
***************
*** 349,369 ****
  
  ;; First define the arithmetic insns.  Note that the 32-bit forms also
  ;; sign-extend.
- 
- ;; Note that we can do sign extensions in both FP and integer registers.
- ;; However, the result must be in the same type of register as the input.
- ;; The register preferencing code can't handle this case very well, so, for
- ;; now, don't let the FP case show up here for preferencing.  Also,
- ;; sign-extends in FP registers take two instructions.
  (define_insn "extendsidi2"
!   [(set (match_operand:DI 0 "register_operand" "=r,r,*f")
! 	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,*f")))]
    ""
    "@
     addl %1,$31,%0
!    ldl %0,%1
!    cvtql %1,%0\;cvtlq %0,%0"
!   [(set_attr "type" "iadd,ild,fadd")])
  
  ;; Do addsi3 the way expand_binop would do if we didn't have one.  This
  ;; generates better code.  We have the anonymous addsi3 pattern below in
--- 349,362 ----
  
  ;; First define the arithmetic insns.  Note that the 32-bit forms also
  ;; sign-extend.
  (define_insn "extendsidi2"
!   [(set (match_operand:DI 0 "register_operand" "=r,r")
! 	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
    ""
    "@
     addl %1,$31,%0
!    ldl %0,%1"
!   [(set_attr "type" "iadd,ild")])
  
  ;; Do addsi3 the way expand_binop would do if we didn't have one.  This
  ;; generates better code.  We have the anonymous addsi3 pattern below in