diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 7743c61e..1ace33a 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -12794,6 +12794,100 @@
   operands[0] = shallow_copy_rtx (operands[0]);
   PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
 })
+
+;; Help combine recognize bt followed by cmov
+(define_split
+  [(set (match_operand:SWI248 0 "register_operand")
+	(if_then_else:SWI248
+	 (ne
+	  (zero_extract:SWI48
+	   (match_operand:SWI48 1 "register_operand")
+	   (const_int 1)
+	   (zero_extend:SI (match_operand:QI 2 "register_operand")))
+	  (const_int 0))
+	 (match_operand:SWI248 3 "nonimmediate_operand")
+	 (match_operand:SWI248 4 "nonimmediate_operand")))]
+  "TARGET_USE_BT && TARGET_CMOVE
+   && !(MEM_P (operands[3]) && MEM_P (operands[4]))
+   && ix86_pre_reload_split ()"
+  [(set (reg:CCC FLAGS_REG)
+	(compare:CCC
+	 (zero_extract:SWI48 (match_dup 1) (const_int 1) (match_dup 2))
+	 (const_int 0)))
+   (set (match_dup 0)
+	(if_then_else:SWI248 (eq (reg:CCC FLAGS_REG) (const_int 0))
+			     (match_dup 3)
+			     (match_dup 4)))]
+{
+  operands[2] = lowpart_subreg (SImode, operands[2], QImode);
+})
+
+;; Help combine recognize bt followed by setc
+(define_insn_and_split "*bt<mode>_setcqi"
+  [(set (subreg:SWI48 (match_operand:QI 0 "register_operand") 0)
+        (zero_extract:SWI48
+         (match_operand:SWI48 1 "register_operand")
+         (const_int 1)
+         (zero_extend:SI (match_operand:QI 2 "register_operand"))))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_USE_BT && ix86_pre_reload_split ()"
+  "#"
+  "&& 1"
+  [(set (reg:CCC FLAGS_REG)
+        (compare:CCC
+         (zero_extract:SWI48 (match_dup 1) (const_int 1) (match_dup 2))
+         (const_int 0)))
+   (set (match_dup 0)
+        (eq:QI (reg:CCC FLAGS_REG) (const_int 0)))]
+{
+  operands[2] = lowpart_subreg (SImode, operands[2], QImode);
+})
+
+;; Help combine recognize bt followed by setnc
+(define_insn_and_split "*bt<mode>_setncqi"
+  [(set (match_operand:QI 0 "register_operand")
+	(and:QI
+	 (not:QI
+	  (subreg:QI
+	   (lshiftrt:SWI48 (match_operand:SWI48 1 "register_operand")
+			   (match_operand:QI 2 "register_operand")) 0))
+	 (const_int 1)))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_USE_BT && ix86_pre_reload_split ()"
+  "#"
+  "&& 1"
+  [(set (reg:CCC FLAGS_REG)
+        (compare:CCC
+         (zero_extract:SWI48 (match_dup 1) (const_int 1) (match_dup 2))
+         (const_int 0)))
+   (set (match_dup 0)
+        (ne:QI (reg:CCC FLAGS_REG) (const_int 0)))]
+{
+  operands[2] = lowpart_subreg (SImode, operands[2], QImode);
+})
+
+(define_insn_and_split "*bt<mode>_setnc<mode>"
+  [(set (match_operand:SWI48 0 "register_operand")
+	(and:SWI48
+	 (not:SWI48
+	  (lshiftrt:SWI48 (match_operand:SWI48 1 "register_operand")
+			  (match_operand:QI 2 "register_operand")))
+	 (const_int 1)))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_USE_BT && ix86_pre_reload_split ()"
+  "#"
+  "&& 1"
+  [(set (reg:CCC FLAGS_REG)
+        (compare:CCC
+         (zero_extract:SWI48 (match_dup 1) (const_int 1) (match_dup 2))
+         (const_int 0)))
+   (set (match_dup 3)
+        (ne:QI (reg:CCC FLAGS_REG) (const_int 0)))
+   (set (match_dup 0) (zero_extend:SWI48 (match_dup 3)))]
+{
+  operands[2] = lowpart_subreg (SImode, operands[2], QImode);
+  operands[3] = gen_reg_rtx (QImode);
+})
 
 ;; Store-flag instructions.