[PATCH] i386: Adjust some c86-4g*.md modeling to reduce build time
Kewen Lin
linkw_gcc@126.com
Fri May 1 08:02:04 GMT 2026
Hi all,
Commit r17-203 caused significant increase in GCC build time
on several environment as folks reported, mainly due to
excessively long execution time of genautomata.
As Alexander pointed out, the current division modeling in
c86-4g*.md can cause a combinatorial explosion in the
automaton, that further leads to significant build time
increase.
Following Alexander's suggestion, this patch introduces the
dedicated automatons and cpu_units for idiv and fdiv, uses
them to updates the integer, floating point division and
square root modeling for now. Some evaluated statistics
are listed below.
With r17-202:
*Tested stage-1 i686 build -j 32: 255 seconds*
$ nm -CS -t d --defined-only gcc/insn-automata.o \
| sed 's/^[0-9]* 0*//' \
| sort -n | tail -20
13896 r slm_transitions
15360 r znver4_fp_store_transitions
16760 r znver4_ieu_transitions
17776 r bdver1_ieu_transitions
20068 r bdver1_fp_check
20068 r bdver1_fp_transitions
20983 t internal_state_transition(int, DFA_chip*)
22270 t internal_min_issue_delay(int, DFA_chip*)
26208 r slm_min_issue_delay
27244 r bdver1_fp_min_issue_delay
28518 r glm_check
28518 r glm_transitions
33690 r geode_min_issue_delay
45436 r znver4_fpu_min_issue_delay
46980 r bdver3_fp_min_issue_delay
49428 r glm_min_issue_delay
53730 r btver2_fp_min_issue_delay
53760 r znver1_fp_transitions
93960 r bdver3_fp_transitions
181744 r znver4_fpu_transitions
With culprit commit r17-203:
*Tested stage-1 i686 build -j 32: 949 seconds*
$ nm -CS -t d --defined-only gcc/insn-automata.o \
| sed 's/^[0-9]* 0*//' \
| sort -n | tail -20
28518 r glm_check
28518 r glm_transitions
33690 r geode_min_issue_delay
45436 r znver4_fpu_min_issue_delay
46980 r bdver3_fp_min_issue_delay
49428 r glm_min_issue_delay
53730 r btver2_fp_min_issue_delay
53760 r znver1_fp_transitions
68160 r c86_4g_ieu_min_issue_delay
93960 r bdver3_fp_transitions
110080 r c86_4g_fp_min_issue_delay
136320 r c86_4g_ieu_transitions
181744 r znver4_fpu_transitions
220160 r c86_4g_fp_transitions
262988 r c86_4g_m7_fpu_base
475225 r c86_4g_m7_ieu_min_issue_delay
950450 r c86_4g_m7_ieu_transitions
4010567 r c86_4g_m7_fpu_min_issue_delay
5496908 r c86_4g_m7_fpu_check
5496908 r c86_4g_m7_fpu_transitions
With this patch:
*Tested stage-1 i686 build -j 32: 257 seconds*
$ nm -CS -t d --defined-only gcc/insn-automata.o \
| sed 's/^[0-9]* 0*//' \
| sort -n | tail -20
20068 r bdver1_fp_transitions
22354 r c86_4g_m7_ieu_min_issue_delay
25705 t internal_state_transition(int, DFA_chip*)
26208 r slm_min_issue_delay
27164 t internal_min_issue_delay(int, DFA_chip*)
27244 r bdver1_fp_min_issue_delay
28518 r glm_check
28518 r glm_transitions
33690 r geode_min_issue_delay
33728 r c86_4g_fp_transitions
45436 r znver4_fpu_min_issue_delay
46980 r bdver3_fp_min_issue_delay
49428 r glm_min_issue_delay
53730 r btver2_fp_min_issue_delay
53760 r znver1_fp_transitions
89414 r c86_4g_m7_ieu_transitions
93960 r bdver3_fp_transitions
181744 r znver4_fpu_transitions
326322 r c86_4g_m7_fpu_min_issue_delay
1305288 r c86_4g_m7_fpu_transitions
I noticed the number of c86_4g_m7_fpu_transitions is still
large, but this patch can address the build time issue.
To avoid impacting folks' daily builds and regular testings,
I'd like to land this patch first if possible. We can then further
refine the c86-4g modeling and investigate large transition
count as part of the follow-up work, even potentially part
of PR 87832.
Any thoughts? It has been bootstrapped and the regression
testing is currently ongoing. Is it ok for trunk if everything
goes well?
@Sam, could you please double-check if this helps on your
build boxes?
Thanks for all inputs, comments and suggestions!
BR,
Kewen
-----
gcc/ChangeLog:
* config/i386/c86-4g-m7.md (c86_4g_m7_idiv): New automaton.
(c86_4g_m7_fdiv): Ditto.
(c86-4g-m7-idiv): New unit.
(c86-4g-m7-fdiv): Ditto.
(c86_4g_m7_idiv_DI): Adjust unit in the reservation.
(c86_4g_m7_idiv_SI): Ditto.
(c86_4g_m7_idiv_HI): Ditto.
(c86_4g_m7_idiv_QI): Ditto.
(c86_4g_m7_idiv_DI_load): Ditto.
(c86_4g_m7_idiv_SI_load): Ditto.
(c86_4g_m7_idiv_HI_load): Ditto.
(c86_4g_m7_idiv_QI_load): Ditto.
(c86_4g_m7_fp_div): Ditto.
(c86_4g_m7_fp_div_load): Ditto.
(c86_4g_m7_fp_idiv_load): Ditto.
(c86_4g_m7_avx512_ssediv): Ditto.
(c86_4g_m7_avx512_ssediv_mem): Ditto.
(c86_4g_m7_avx512_ssediv_z): Ditto.
(c86_4g_m7_avx512_ssediv_zmem): Ditto.
(c86_4g_m7_avx512_sse_sqrt): Ditto.
(c86_4g_m7_avx512_sse_sqrt_load): Ditto.
(c86_4g_m7_fp_sqrt): Ditto. Rename from ...
(c86_4g_m7fp_sqrt): ... here.
* config/i386/c86-4g.md (c86_4g_idiv): New automaton.
(c86_4g_fdiv): Ditto.
(c86-4g-idiv): New unit.
(c86-4g-fdiv): Ditto.
(c86_4g_idiv_DI): Adjust unit in the reservation.
(c86_4g_idiv_SI): Ditto.
(c86_4g_idiv_HI): Ditto.
(c86_4g_idiv_QI): Ditto.
(c86_4g_idiv_mem_DI): Ditto.
(c86_4g_idiv_mem_SI): Ditto.
(c86_4g_idiv_mem_HI): Ditto.
(c86_4g_idiv_mem_QI): Ditto.
(c86_4g_fp_sqrt): Ditto.
(c86_4g_sse_sqrt_sf): Ditto.
(c86_4g_sse_sqrt_sf_mem): Ditto.
(c86_4g_sse_sqrt_df): Ditto.
(c86_4g_sse_sqrt_df_mem): Ditto.
(c86_4g_fp_op_div): Ditto.
(c86_4g_fp_op_div_load): Ditto.
(c86_4g_fp_op_idiv_load): Ditto.
(c86_4g_ssediv_ss_ps): Ditto.
(c86_4g_ssediv_ss_ps_load): Ditto.
(c86_4g_ssediv_ss_pd): Ditto.
(c86_4g_ssediv_ss_pd_load): Ditto.
(c86_4g_ssediv_avx256_ps): Ditto.
(c86_4g_ssediv_avx256_ps_load): Ditto.
(c86_4g_ssediv_avx256_pd): Ditto.
(c86_4g_ssediv_avx256_pd_load): Ditto.
Signed-off-by: Kewen Lin <linkewen@hygon.cn>
---
gcc/config/i386/c86-4g-m7.md | 45 +++++++++++++++-------------
gcc/config/i386/c86-4g.md | 57 ++++++++++++++++++++----------------
2 files changed, 56 insertions(+), 46 deletions(-)
diff --git a/gcc/config/i386/c86-4g-m7.md b/gcc/config/i386/c86-4g-m7.md
index 7eda123acaa..a3701460697 100644
--- a/gcc/config/i386/c86-4g-m7.md
+++ b/gcc/config/i386/c86-4g-m7.md
@@ -19,8 +19,9 @@
;; HYGON c86-4g-m7 Scheduling
;; Modeling automatons for decoders, integer execution pipes,
-;; AGU pipes, branch, floating point execution and fp store units.
-(define_automaton "c86_4g_m7, c86_4g_m7_ieu, c86_4g_m7_agu, c86_4g_m7_fpu")
+;; AGU pipes, branch, floating point execution, fp store units,
+;; integer and floating point dividers.
+(define_automaton "c86_4g_m7, c86_4g_m7_ieu, c86_4g_m7_agu, c86_4g_m7_fpu, c86_4g_m7_idiv, c86_4g_m7_fdiv")
;; Decoders unit has 4 decoders and all of them can decode fast path
;; and vector type instructions.
@@ -29,6 +30,10 @@ (define_cpu_unit "c86-4g-m7-decode1" "c86_4g_m7")
(define_cpu_unit "c86-4g-m7-decode2" "c86_4g_m7")
(define_cpu_unit "c86-4g-m7-decode3" "c86_4g_m7")
+;; Two separated dividers for int and fp.
+(define_cpu_unit "c86-4g-m7-idiv" "c86_4g_m7_idiv")
+(define_cpu_unit "c86-4g-m7-fdiv" "c86_4g_m7_fdiv")
+
;; Currently blocking all decoders for vector path instructions as
;; they are dispatched separetely as microcode sequence.
(define_reservation "c86-4g-m7-vector" "c86-4g-m7-decode0+c86-4g-m7-decode1+c86-4g-m7-decode2+c86-4g-m7-decode3")
@@ -168,56 +173,56 @@ (define_insn_reservation "c86_4g_m7_idiv_DI" 41
(and (eq_attr "type" "idiv")
(and (eq_attr "mode" "DI")
(eq_attr "memory" "none"))))
- "c86-4g-m7-double,c86-4g-m7-ieu3*41")
+ "c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*41")
(define_insn_reservation "c86_4g_m7_idiv_SI" 25
(and (eq_attr "cpu" "c86_4g_m7")
(and (eq_attr "type" "idiv")
(and (eq_attr "mode" "SI")
(eq_attr "memory" "none"))))
- "c86-4g-m7-double,c86-4g-m7-ieu3*25")
+ "c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*25")
(define_insn_reservation "c86_4g_m7_idiv_HI" 17
(and (eq_attr "cpu" "c86_4g_m7")
(and (eq_attr "type" "idiv")
(and (eq_attr "mode" "HI")
(eq_attr "memory" "none"))))
- "c86-4g-m7-double,c86-4g-m7-ieu3*17")
+ "c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*17")
(define_insn_reservation "c86_4g_m7_idiv_QI" 15
(and (eq_attr "cpu" "c86_4g_m7")
(and (eq_attr "type" "idiv")
(and (eq_attr "mode" "QI")
(eq_attr "memory" "none"))))
- "c86-4g-m7-direct,c86-4g-m7-ieu3*15")
+ "c86-4g-m7-direct,c86-4g-m7-ieu3,c86-4g-m7-idiv*15")
(define_insn_reservation "c86_4g_m7_idiv_DI_load" 45
(and (eq_attr "cpu" "c86_4g_m7")
(and (eq_attr "type" "idiv")
(and (eq_attr "mode" "DI")
(eq_attr "memory" "load"))))
- "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3*41")
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*41")
(define_insn_reservation "c86_4g_m7_idiv_SI_load" 29
(and (eq_attr "cpu" "c86_4g_m7")
(and (eq_attr "type" "idiv")
(and (eq_attr "mode" "SI")
(eq_attr "memory" "load"))))
- "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3*25")
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*25")
(define_insn_reservation "c86_4g_m7_idiv_HI_load" 21
(and (eq_attr "cpu" "c86_4g_m7")
(and (eq_attr "type" "idiv")
(and (eq_attr "mode" "HI")
(eq_attr "memory" "load"))))
- "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3*17")
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*17")
(define_insn_reservation "c86_4g_m7_idiv_QI_load" 19
(and (eq_attr "cpu" "c86_4g_m7")
(and (eq_attr "type" "idiv")
(and (eq_attr "mode" "QI")
(eq_attr "memory" "load"))))
- "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu3*15")
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*15")
;; Integer/genaral Instructions
(define_insn_reservation "c86_4g_m7_insn" 1
@@ -439,7 +444,7 @@ (define_insn_reservation "c86_4g_m7fp_sqrt" 22
(and (eq_attr "cpu" "c86_4g_m7")
(and (eq_attr "type" "fpspc")
(eq_attr "c86_attr" "sqrt")))
- "c86-4g-m7-direct,c86-4g-m7-fpu1*22")
+ "c86-4g-m7-direct,c86-4g-m7-fpu1,c86-4g-m7-fdiv*22")
;; FPSPC
(define_insn_reservation "c86_4g_m7_fp_spc_direct" 5
@@ -482,21 +487,21 @@ (define_insn_reservation "c86_4g_m7_fp_div" 15
(and (eq_attr "cpu" "c86_4g_m7")
(and (eq_attr "type" "fdiv")
(eq_attr "memory" "none")))
- "c86-4g-m7-direct,c86-4g-m7-fpu1*7")
+ "c86-4g-m7-direct,c86-4g-m7-fpu1,c86-4g-m7-fdiv*15")
(define_insn_reservation "c86_4g_m7_fp_div_load" 22
(and (eq_attr "cpu" "c86_4g_m7")
(and (eq_attr "type" "fdiv")
(and (eq_attr "fp_int_src" "false")
(eq_attr "memory" "!none"))))
- "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1*7")
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1,c86-4g-m7-fdiv*15")
(define_insn_reservation "c86_4g_m7_fp_idiv_load" 26
(and (eq_attr "cpu" "c86_4g_m7")
(and (eq_attr "type" "fdiv")
(and (eq_attr "fp_int_src" "true")
(eq_attr "memory" "!none"))))
- "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1*7")
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1,c86-4g-m7-fdiv*15")
(define_insn_reservation "c86_4g_m7_fp_fsgn" 1
(and (eq_attr "cpu" "c86_4g_m7")
@@ -1531,28 +1536,28 @@ (define_insn_reservation "c86_4g_m7_avx512_ssediv" 13
(and (eq_attr "type" "ssediv")
(and (not (eq_attr "mode" "V16SF,V8DF"))
(eq_attr "memory" "none"))))
- "c86-4g-m7-direct,c86-4g-m7-fpu3*7")
+ "c86-4g-m7-direct,c86-4g-m7-fpu3,c86-4g-m7-fdiv*13")
(define_insn_reservation "c86_4g_m7_avx512_ssediv_mem" 20
(and (eq_attr "cpu" "c86_4g_m7")
(and (eq_attr "type" "ssediv")
(and (not (eq_attr "mode" "V16SF,V8DF"))
(eq_attr "memory" "load"))))
- "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu3*7")
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu3,c86-4g-m7-fdiv*13")
(define_insn_reservation "c86_4g_m7_avx512_ssediv_z" 24
(and (eq_attr "cpu" "c86_4g_m7")
(and (eq_attr "type" "ssediv")
(and (eq_attr "mode" "V16SF,V8DF")
(eq_attr "memory" "none"))))
- "c86-4g-m7-double,c86-4g-m7-fpu3*7")
+ "c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fdiv*24")
(define_insn_reservation "c86_4g_m7_avx512_ssediv_zmem" 31
(and (eq_attr "cpu" "c86_4g_m7")
(and (eq_attr "type" "ssediv")
(and (eq_attr "mode" "V16SF,V8DF")
(eq_attr "memory" "load"))))
- "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu3*7")
+ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu3,c86-4g-m7-fdiv*24")
;; SSECMP
(define_insn_reservation "c86_4g_m7_avx512_ssecmp" 5
@@ -1932,14 +1937,14 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt" 16
(and (eq_attr "type" "sse")
(and (eq_attr "c86_attr" "sqrt")
(eq_attr "memory" "none"))))
- "c86-4g-m7-direct,c86-4g-m7-fpu1*7|c86-4g-m7-fpu3*7")
+ "c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu3,c86-4g-m7-fdiv*16")
(define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_load" 23
(and (eq_attr "cpu" "c86_4g_m7")
(and (eq_attr "type" "sse")
(and (eq_attr "c86_attr" "sqrt")
(eq_attr "memory" "load"))))
- "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1*7|c86-4g-m7-fpu3*7")
+ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1|c86-4g-m7-fpu3,c86-4g-m7-fdiv*16")
;; MSKLOG/MSKMOV
(define_insn_reservation "c86_4g_m7_avx512_msklog" 1
diff --git a/gcc/config/i386/c86-4g.md b/gcc/config/i386/c86-4g.md
index 66c4e2cf744..49a46a8aa19 100644
--- a/gcc/config/i386/c86-4g.md
+++ b/gcc/config/i386/c86-4g.md
@@ -29,8 +29,9 @@ (define_attr "c86_attr" "other,abs,sqrt,maxmin,blend,blendv,rcp,movnt,avg,
;; HYGON Scheduling
;; Modeling automatons for decoders, integer execution pipes,
-;; AGU pipes and floating point execution units.
-(define_automaton "c86_4g, c86_4g_ieu, c86_4g_fp, c86_4g_agu")
+;; AGU pipes, floating point execution units, integer and
+;; floating point dividers.
+(define_automaton "c86_4g, c86_4g_ieu, c86_4g_fp, c86_4g_agu, c86_4g_idiv, c86_4g_fdiv")
;; Decoders unit has 4 decoders and all of them can decode fast path
;; and vector type instructions.
@@ -39,6 +40,10 @@ (define_cpu_unit "c86-4g-decode1" "c86_4g")
(define_cpu_unit "c86-4g-decode2" "c86_4g")
(define_cpu_unit "c86-4g-decode3" "c86_4g")
+;; Two separated dividers for int and fp.
+(define_cpu_unit "c86-4g-idiv" "c86_4g_idiv")
+(define_cpu_unit "c86-4g-fdiv" "c86_4g_fdiv")
+
;; Currently blocking all decoders for vector path instructions as
;; they are dispatched separetely as microcode sequence.
;; Fix me: Need to revisit this.
@@ -146,28 +151,28 @@ (define_insn_reservation "c86_4g_idiv_DI" 41
(and (eq_attr "type" "idiv")
(and (eq_attr "mode" "DI")
(eq_attr "memory" "none"))))
- "c86-4g-double,c86-4g-ieu2*41")
+ "c86-4g-double,c86-4g-ieu2,c86-4g-idiv*41")
(define_insn_reservation "c86_4g_idiv_SI" 25
(and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
(and (eq_attr "type" "idiv")
(and (eq_attr "mode" "SI")
(eq_attr "memory" "none"))))
- "c86-4g-double,c86-4g-ieu2*25")
+ "c86-4g-double,c86-4g-ieu2,c86-4g-idiv*25")
(define_insn_reservation "c86_4g_idiv_HI" 17
(and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
(and (eq_attr "type" "idiv")
(and (eq_attr "mode" "HI")
(eq_attr "memory" "none"))))
- "c86-4g-double,c86-4g-ieu2*17")
+ "c86-4g-double,c86-4g-ieu2,c86-4g-idiv*17")
(define_insn_reservation "c86_4g_idiv_QI" 15
(and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
(and (eq_attr "type" "idiv")
(and (eq_attr "mode" "QI")
(eq_attr "memory" "none"))))
- "c86-4g-direct,c86-4g-ieu2*15")
+ "c86-4g-direct,c86-4g-ieu2,c86-4g-idiv*15")
;; Mem operands
(define_insn_reservation "c86_4g_idiv_mem_DI" 45
@@ -175,28 +180,28 @@ (define_insn_reservation "c86_4g_idiv_mem_DI" 45
(and (eq_attr "type" "idiv")
(and (eq_attr "mode" "DI")
(eq_attr "memory" "load"))))
- "c86-4g-double,c86-4g-load,c86-4g-ieu2*41")
+ "c86-4g-double,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*41")
(define_insn_reservation "c86_4g_idiv_mem_SI" 29
(and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
(and (eq_attr "type" "idiv")
(and (eq_attr "mode" "SI")
(eq_attr "memory" "load"))))
- "c86-4g-double,c86-4g-load,c86-4g-ieu2*25")
+ "c86-4g-double,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*25")
(define_insn_reservation "c86_4g_idiv_mem_HI" 21
(and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
(and (eq_attr "type" "idiv")
(and (eq_attr "mode" "HI")
(eq_attr "memory" "load"))))
- "c86-4g-double,c86-4g-load,c86-4g-ieu2*17")
+ "c86-4g-double,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*17")
(define_insn_reservation "c86_4g_idiv_mem_QI" 19
(and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
(and (eq_attr "type" "idiv")
(and (eq_attr "mode" "QI")
(eq_attr "memory" "load"))))
- "c86-4g-direct,c86-4g-load,c86-4g-ieu2*15")
+ "c86-4g-direct,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*15")
;; STR ISHIFT which are micro coded.
;; Fix me: Latency need to be rechecked.
@@ -382,7 +387,7 @@ (define_insn_reservation "c86_4g_fp_sqrt" 22
(and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
(and (eq_attr "type" "fpspc")
(eq_attr "c86_attr" "sqrt")))
- "c86-4g-direct,c86-4g-fp1*22")
+ "c86-4g-direct,c86-4g-fp1,c86-4g-fdiv*22")
(define_insn_reservation "c86_4g_sse_sqrt_sf" 14
(and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
@@ -390,7 +395,7 @@ (define_insn_reservation "c86_4g_sse_sqrt_sf" 14
(and (eq_attr "memory" "none,unknown")
(and (eq_attr "c86_attr" "sqrt")
(eq_attr "type" "sse")))))
- "c86-4g-direct,c86-4g-fp1*14")
+ "c86-4g-direct,c86-4g-fp1,c86-4g-fdiv*14")
(define_insn_reservation "c86_4g_sse_sqrt_sf_mem" 21
(and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
@@ -398,7 +403,7 @@ (define_insn_reservation "c86_4g_sse_sqrt_sf_mem" 21
(and (eq_attr "memory" "load")
(and (eq_attr "c86_attr" "sqrt")
(eq_attr "type" "sse")))))
- "c86-4g-direct,c86-4g-load,c86-4g-fp1*14")
+ "c86-4g-direct,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*14")
(define_insn_reservation "c86_4g_sse_sqrt_df" 20
(and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
@@ -406,7 +411,7 @@ (define_insn_reservation "c86_4g_sse_sqrt_df" 20
(and (eq_attr "memory" "none,unknown")
(and (eq_attr "c86_attr" "sqrt")
(eq_attr "type" "sse")))))
- "c86-4g-direct,c86-4g-fp1*20")
+ "c86-4g-direct,c86-4g-fp1,c86-4g-fdiv*20")
(define_insn_reservation "c86_4g_sse_sqrt_df_mem" 27
(and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
@@ -414,7 +419,7 @@ (define_insn_reservation "c86_4g_sse_sqrt_df_mem" 27
(and (eq_attr "memory" "load")
(and (eq_attr "c86_attr" "sqrt")
(eq_attr "type" "sse")))))
- "c86-4g-direct,c86-4g-load,c86-4g-fp1*20")
+ "c86-4g-direct,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*20")
;; RCP
(define_insn_reservation "c86_4g_sse_rcp" 5
@@ -487,20 +492,20 @@ (define_insn_reservation "c86_4g_fp_op_div" 15
(and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
(and (eq_attr "type" "fdiv")
(eq_attr "memory" "none")))
- "c86-4g-direct,c86-4g-fp1*15")
+ "c86-4g-direct,c86-4g-fp1,c86-4g-fdiv*15")
(define_insn_reservation "c86_4g_fp_op_div_load" 22
(and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
(and (eq_attr "type" "fdiv")
(eq_attr "memory" "load")))
- "c86-4g-direct,c86-4g-load,c86-4g-fp1*15")
+ "c86-4g-direct,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*15")
(define_insn_reservation "c86_4g_fp_op_idiv_load" 27
(and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
(and (eq_attr "type" "fdiv")
(and (eq_attr "fp_int_src" "true")
(eq_attr "memory" "load"))))
- "c86-4g-double,c86-4g-load,c86-4g-fp1*19")
+ "c86-4g-double,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*19")
;; MMX, SSE, SSEn.n, AVX, AVX2 instructions
(define_insn_reservation "c86_4g_fp_insn" 1
@@ -1019,28 +1024,28 @@ (define_insn_reservation "c86_4g_ssediv_ss_ps" 10
(eq_attr "mode" "V4SF,SF"))
(and (eq_attr "type" "ssediv")
(eq_attr "memory" "none")))
- "c86-4g-direct,c86-4g-fp1*10")
+ "c86-4g-direct,c86-4g-fp1,c86-4g-fdiv*10")
(define_insn_reservation "c86_4g_ssediv_ss_ps_load" 17
(and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
(eq_attr "mode" "V4SF,SF"))
(and (eq_attr "type" "ssediv")
(eq_attr "memory" "load")))
- "c86-4g-direct,c86-4g-load,c86-4g-fp1*10")
+ "c86-4g-direct,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*10")
(define_insn_reservation "c86_4g_ssediv_sd_pd" 13
(and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
(eq_attr "mode" "V2DF,DF"))
(and (eq_attr "type" "ssediv")
(eq_attr "memory" "none")))
- "c86-4g-direct,c86-4g-fp1*13")
+ "c86-4g-direct,c86-4g-fp1,c86-4g-fdiv*13")
(define_insn_reservation "c86_4g_ssediv_sd_pd_load" 20
(and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
(eq_attr "mode" "V2DF,DF"))
(and (eq_attr "type" "ssediv")
(eq_attr "memory" "load")))
- "c86-4g-direct,c86-4g-load,c86-4g-fp1*13")
+ "c86-4g-direct,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*13")
(define_insn_reservation "c86_4g_ssediv_avx256_ps" 10
@@ -1048,28 +1053,28 @@ (define_insn_reservation "c86_4g_ssediv_avx256_ps" 10
(and (eq_attr "mode" "V8SF")
(and (eq_attr "memory" "none")
(eq_attr "type" "ssediv"))))
- "c86-4g-double,c86-4g-fp1*10")
+ "c86-4g-double,c86-4g-fp1,c86-4g-fdiv*10")
(define_insn_reservation "c86_4g_ssediv_avx256_ps_load" 17
(and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
(and (eq_attr "mode" "V8SF")
(and (eq_attr "type" "ssediv")
(eq_attr "memory" "load"))))
- "c86-4g-double,c86-4g-load,c86-4g-fp1*10")
+ "c86-4g-double,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*10")
(define_insn_reservation "c86_4g_ssediv_avx256_pd" 13
(and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
(and (eq_attr "mode" "V4DF")
(and (eq_attr "type" "ssediv")
(eq_attr "memory" "none"))))
- "c86-4g-double,c86-4g-fp1*13")
+ "c86-4g-double,c86-4g-fp1,c86-4g-fdiv*13")
(define_insn_reservation "c86_4g_ssediv_avx256_pd_load" 20
(and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
(and (eq_attr "mode" "V4DF")
(and (eq_attr "type" "ssediv")
(eq_attr "memory" "load"))))
- "c86-4g-double,c86-4g-load,c86-4g-fp1*13")
+ "c86-4g-double,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*13")
;; SSE MUL
(define_insn_reservation "c86_4g_ssemul_ss_ps" 3
(and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
--
2.34.1
More information about the Gcc-patches
mailing list