[PATCH v2 7/9] Add more MIPS Allegrex VFPU instructions
David Guillen Fandos
david@davidgf.net
Tue Jan 20 23:32:15 GMT 2026
Add move instructions (such as from/to GPR moves), load immediate
instructions (including a 16bit float immediate load), some scaling
instructions that use small immediates and some other missing
instructions that move/scale registers or generate values (random
generator instructions).
Signed-off-by: David Guillen Fandos <david@davidgf.net>
---
gas/config/tc-mips.c | 58 ++++++++++++++
gas/testsuite/gas/mips/allegrex-vfpu-errors.l | 15 ++++
gas/testsuite/gas/mips/allegrex-vfpu-errors.s | 15 ++++
gas/testsuite/gas/mips/allegrex-vfpu.d | 72 +++++++++++++++++
gas/testsuite/gas/mips/allegrex-vfpu.s | 73 ++++++++++++++++++
include/opcode/mips.h | 20 +++++
opcodes/mips-dis.c | 42 ++++++++++
opcodes/mips-formats.h | 8 ++
opcodes/mips-opc.c | 77 +++++++++++++++++++
9 files changed, 380 insertions(+)
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 5a42bd7fc28..3541179caf8 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -5321,6 +5321,7 @@ operand_reg_mask (const struct mips_cl_insn *insn,
case OP_VU0_MATCH_SUFFIX:
case OP_VFPU_REG:
case OP_VFPU_PFX:
+ case OP_VFPU_IMM:
case OP_IMM_INDEX:
abort ();
@@ -7165,6 +7166,58 @@ match_vfpu_reg_operand (struct mips_arg_info *arg,
return true;
}
+/* Matches VFPU immediate operands. */
+static bfd_boolean
+match_vfpu_imm_operand (struct mips_arg_info *arg,
+ const struct mips_operand *operand)
+{
+ unsigned int uval;
+ const struct mips_vfpu_imm_operand *immvfpuop;
+ immvfpuop = (struct mips_vfpu_imm_operand*)operand;
+
+ switch (immvfpuop->immtype)
+ {
+ case OP_VFPU_FP16:
+ if (arg->token->type == OT_FLOAT && arg->token->u.flt.length == 4)
+ {
+ unsigned int f32 = target_big_endian
+ ? bfd_getb32 (arg->token->u.flt.data)
+ : bfd_getl32 (arg->token->u.flt.data);
+ unsigned int sign = (f32 >> 31) & 1;
+ unsigned int expn = (f32 >> 23) & 0xff;
+ unsigned int mant = f32 & 0x7fffff;
+ /* Check if the immediate is infinited or NaN and re-encode them. */
+ if (expn == 255)
+ uval = (sign << 15) | (0x1f << 10) | (mant ? 1 : 0);
+ /* Any number that's too small to represent is rounded to zero. */
+ else if (expn <= 127 - 15)
+ {
+ if (mant)
+ as_warn (_("immediate value too small for float16!"));
+ uval = (sign << 15);
+ }
+ else if (expn >= 127 + 15)
+ {
+ as_warn (_("immediate value too big for float16!"));
+ uval = (sign << 15) | (0x1f << 10);
+ }
+ else
+ {
+ unsigned int nexp = expn - 127 + 15;
+ unsigned int nmnt = mant >> (23 - 10);
+ uval = (sign << 15) | (nexp << 10) | nmnt;
+ }
+
+ insn_insert_operand (arg->insn, operand, uval);
+ ++arg->token;
+ return true;
+ }
+ }
+
+ return false;
+}
+
+
/* Try to match a token from ARG against OPERAND. Consume the token
and return true on success, otherwise return false. */
@@ -7238,6 +7291,9 @@ match_operand (struct mips_arg_info *arg,
case OP_VFPU_PFX:
return match_vfpu_prefix_operand (arg, operand);
+ case OP_VFPU_IMM:
+ return match_vfpu_imm_operand (arg, operand);
+
case OP_IMM_INDEX:
return match_imm_index_operand (arg, operand);
@@ -15288,6 +15344,8 @@ mips_ip (char *str, struct mips_cl_insn *insn)
format = 'f';
else if (strcmp (first->name, "li.d") == 0)
format = 'd';
+ else if (strcmp (first->name, "vfim.s") == 0)
+ format = 'f';
else
format = 0;
tokens = mips_parse_arguments (str + end, format, first);
diff --git a/gas/testsuite/gas/mips/allegrex-vfpu-errors.l b/gas/testsuite/gas/mips/allegrex-vfpu-errors.l
index 918979627d5..79f3a199e55 100644
--- a/gas/testsuite/gas/mips/allegrex-vfpu-errors.l
+++ b/gas/testsuite/gas/mips/allegrex-vfpu-errors.l
@@ -66,3 +66,18 @@
.*:68: Error: Invalid dest and source register overlap \(identical overlap is allowed\) `vmscl.q M000,E000,S100'
.*:69: Error: Invalid dest and source register overlap \(no overlap is allowed\) `vtfm2.p R000,M000,R200'
.*:70: Error: Invalid dest and target register overlap \(no overlap is allowed\) `vtfm2.p R000,M200,R000'
+.*:71: Error: operand 3 out of range `vwbn.s S000,S733,0x123'
+.*:72: Error: operand 2 out of range `viim.s S123,100000'
+.*:73: Warning: immediate value too big for float16!
+.*:74: Warning: immediate value too small for float16!
+.*:75: Error: no prefixes allowed for s-register `vsrt1.q R000,R000\[x,x,y,y\]'
+.*:76: Error: no prefixes allowed for s-register `vsrt2.q R000,R000\[x,x,y,y\]'
+.*:77: Error: no prefixes allowed for s-register `vsrt3.q R000,R000\[x,x,y,y\]'
+.*:78: Error: no prefixes allowed for s-register `vsrt4.q R000,R000\[x,x,y,y\]'
+.*:79: Error: no prefixes allowed for d-register `vrndf1.q R000\[m,,,m\]'
+.*:80: Error: no prefixes allowed for d-register `vrndf2.q R000\[m,m,,m\]'
+.*:81: Error: no prefixes allowed for d-register `vrndi.q R000\[m,,m,m\]'
+.*:82: Error: no prefixes allowed for s-register `vbfy1.q R000,R000\[x,x,y,y\]'
+.*:83: Error: no prefixes allowed for s-register `vbfy2.q R000,R000\[x,x,y,y\]'
+.*:84: Error: invalid source prefix \(only swizzle allowed\) `vi2c.q R000,R000\[-x,-y,-z,-w\]'
+.*:85: Error: invalid source prefix \(only swizzle allowed\) `vi2uc.q R000,R000\[-x,-y,-z,-w\]'
diff --git a/gas/testsuite/gas/mips/allegrex-vfpu-errors.s b/gas/testsuite/gas/mips/allegrex-vfpu-errors.s
index 5d3bbb59375..ce8d53a2285 100644
--- a/gas/testsuite/gas/mips/allegrex-vfpu-errors.s
+++ b/gas/testsuite/gas/mips/allegrex-vfpu-errors.s
@@ -68,6 +68,21 @@
vmscl.q M000, E000, S100
vtfm2.p R000, M000, R200
vtfm2.p R000, M200, R000
+ vwbn.s S000, S733, 0x123
+ viim.s S123, 100000
+ vfim.s S123, 10000000
+ vfim.s S123, 0.000001
+ vsrt1.q R000, R000[x,x,y,y]
+ vsrt2.q R000, R000[x,x,y,y]
+ vsrt3.q R000, R000[x,x,y,y]
+ vsrt4.q R000, R000[x,x,y,y]
+ vrndf1.q R000[m,,,m]
+ vrndf2.q R000[m,m,,m]
+ vrndi.q R000[m,,m,m]
+ vbfy1.q R000, R000[x,x,y,y]
+ vbfy2.q R000, R000[x,x,y,y]
+ vi2c.q R000, R000[-x,-y,-z,-w]
+ vi2uc.q R000, R000[-x,-y,-z,-w]
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
diff --git a/gas/testsuite/gas/mips/allegrex-vfpu.d b/gas/testsuite/gas/mips/allegrex-vfpu.d
index b6cb66d5f8c..b0c6191e61c 100644
--- a/gas/testsuite/gas/mips/allegrex-vfpu.d
+++ b/gas/testsuite/gas/mips/allegrex-vfpu.d
@@ -203,4 +203,76 @@ Disassembly of section .text:
0x00000308 f0a80468 vhtfm2.p R220.p,M100.p,R200.p
0x0000030c f1280480 vhtfm3.t C000.t,M100.t,R200.t
0x00000310 f1a88400 vhtfm4.q C000.q,M100.q,R200.q
+0x00000314 4864007f mfv \$4,S733.s
+0x00000318 48e40066 mtv \$4,S123.s
+0x0000031c d04200a0 vbfy1.p R000.p,C000.p
+0x00000320 d04280a0 vbfy1.q R000.q,C000.q
+0x00000324 d04380a0 vbfy2.q R000.q,C000.q
+0x00000328 d0396220 vc2i.s R000.q,S023.s
+0x0000032c 67200080 vdet.p S000.s,C000.p,R000.p
+0x00000330 d03224e6 vf2h.p S123.s,R100.p
+0x00000334 d032a4e6 vf2h.q R122.p,R100.q
+0x00000338 d26f1c1c vf2id.s S700.s,S700.s,15
+0x0000033c d2601cbc vf2id.p R700.p,C700.p,0
+0x00000340 d27f9c3c vf2id.t R700.t,C700.t,31
+0x00000344 d27e9cbc vf2id.q R700.q,C700.q,30
+0x00000348 d20f1c1c vf2in.s S700.s,S700.s,15
+0x0000034c d2001cbc vf2in.p R700.p,C700.p,0
+0x00000350 d21f9c3c vf2in.t R700.t,C700.t,31
+0x00000354 d2019cbc vf2in.q R700.q,C700.q,1
+0x00000358 d24f1c1c vf2iu.s S700.s,S700.s,15
+0x0000035c d2401cbc vf2iu.p R700.p,C700.p,0
+0x00000360 d25f9c3c vf2iu.t R700.t,C700.t,31
+0x00000364 d2419cbc vf2iu.q R700.q,C700.q,1
+0x00000368 d22f1c1c vf2iz.s S700.s,S700.s,15
+0x0000036c d2201cbc vf2iz.p R700.p,C700.p,0
+0x00000370 d23f9c3c vf2iz.t R700.t,C700.t,31
+0x00000374 d2219cbc vf2iz.q R700.q,C700.q,1
+0x00000378 dfeb5801 vfim.s S233.s,128.125
+0x0000037c dfeb8000 vfim.s S233.s,-0
+0x00000380 dfebfc00 vfim.s S233.s,-inf
+0x00000384 dfebfc01 vfim.s S233.s,-nan
+0x00000388 d03300a0 vh2f.p R000.q,C000.p
+0x0000038c d0330020 vh2f.s R000.p,S000.s
+0x00000390 66002080 vhdp.p S000.s,R000.p,C000.p
+0x00000394 6600a000 vhdp.t S000.s,R000.t,C000.t
+0x00000398 6600a080 vhdp.q S000.s,R000.q,C000.q
+0x0000039c d03d80a0 vi2c.q R000.p,C000.q
+0x000003a0 d2810000 vi2f.s S000.s,S000.s,1
+0x000003a4 d28f00a0 vi2f.p R000.p,C000.p,15
+0x000003a8 d29f8020 vi2f.t R000.t,C000.t,31
+0x000003ac d28080a0 vi2f.q R000.q,C000.q,0
+0x000003b0 d03f0080 vi2s.p S000.s,C000.p
+0x000003b4 d03f80a0 vi2s.q R000.p,C000.q
+0x000003b8 d03c9cbc vi2uc.q R700.p,C700.q
+0x000003bc df667530 viim.s S123.s,30000
+0x000003c0 df668ad0 viim.s S123.s,-30000
+0x000003c4 d0372e66 vlgb.s S123.s,S321.s
+0x000003c8 d0220066 vrndf1.s S123.s
+0x000003cc d02200e0 vrndf1.p R020.p
+0x000003d0 d0228060 vrndf1.t R010.t
+0x000003d4 d0228084 vrndf1.q C100.q
+0x000003d8 d0230066 vrndf2.s S123.s
+0x000003dc d02300e0 vrndf2.p R020.p
+0x000003e0 d0238060 vrndf2.t R010.t
+0x000003e4 d02380a4 vrndf2.q R100.q
+0x000003e8 d0210046 vrndi.s S122.s
+0x000003ec d02100e6 vrndi.p R122.p
+0x000003f0 d0218066 vrndi.t R112.t
+0x000003f4 d0218080 vrndi.q C000.q
+0x000003f8 d0207f00 vrnds.s S733.s
+0x000003fc d03b7cbc vs2i.p R700.q,R720.p
+0x00000400 d03b1e3c vs2i.s R700.p,S720.s
+0x00000404 61732e66 vsbn.s S123.s,S321.s,S433.s
+0x00000408 d0362e66 vsbz.s S123.s,S321.s
+0x0000040c d04520a0 vsocp.p R000.q,R000.p
+0x00000410 d0450020 vsocp.s R000.p,S000.s
+0x00000414 d04080a0 vsrt1.q R000.q,C000.q
+0x00000418 d04180a0 vsrt2.q R000.q,C000.q
+0x0000041c d04880a0 vsrt3.q R000.q,C000.q
+0x00000420 d04980a0 vsrt4.q R000.q,C000.q
+0x00000424 d0387e3c vuc2ifs.s R700.q,S723.s
+0x00000428 d03a7cbc vus2i.p R700.q,R720.p
+0x0000042c d03a1e3c vus2i.s R700.p,S720.s
+0x00000430 d39b2e66 vwbn.s S123.s,S321.s,0x9b
\.\.\.
diff --git a/gas/testsuite/gas/mips/allegrex-vfpu.s b/gas/testsuite/gas/mips/allegrex-vfpu.s
index f649b53d00a..4299a1b020a 100644
--- a/gas/testsuite/gas/mips/allegrex-vfpu.s
+++ b/gas/testsuite/gas/mips/allegrex-vfpu.s
@@ -191,6 +191,79 @@
vhtfm3.t C000, M100, R200
vhtfm4.q C000, M100, R200
+ mfv $4, S733
+ mtv $4, S123
+ vbfy1.p R000, C000
+ vbfy1.q R000, C000
+ vbfy2.q R000, C000
+ vc2i.s R000, S023
+ vdet.p S000, C000, R000
+ vf2h.p S123, R100
+ vf2h.q R122, R100
+ vf2id.s S700,S700,15
+ vf2id.p R700,C700,0
+ vf2id.t R700,C700,31
+ vf2id.q R700,C700,30
+ vf2in.s S700,S700,15
+ vf2in.p R700,C700,0
+ vf2in.t R700,C700,31
+ vf2in.q R700,C700,1
+ vf2iu.s S700,S700,15
+ vf2iu.p R700,C700,0
+ vf2iu.t R700,C700,31
+ vf2iu.q R700,C700,1
+ vf2iz.s S700,S700,15
+ vf2iz.p R700,C700,0
+ vf2iz.t R700,C700,31
+ vf2iz.q R700,C700,1
+ vfim.s S233, 128.125
+ vfim.s S233, -0
+ vfim.s S233, -inf
+ vfim.s S233, -nan
+ vh2f.p R000, C000
+ vh2f.s R000, S000
+ vhdp.p S000, R000, C000
+ vhdp.t S000, R000, C000
+ vhdp.q S000, R000, C000
+ vi2c.q R000.p, C000.q
+ vi2f.s S000.s, S000.s, 1
+ vi2f.p R000.p, C000.p, 15
+ vi2f.t R000.t, C000.t, 31
+ vi2f.q R000.q, C000.q, 0
+ vi2s.p S000.s, C000.p
+ vi2s.q R000.p, C000.q
+ vi2uc.q R700.p, C700.q
+ viim.s S123, 30000
+ viim.s S123, -30000
+ vlgb.s S123, S321
+ vrndf1.s S123
+ vrndf1.p R020
+ vrndf1.t R010
+ vrndf1.q C100
+ vrndf2.s S123
+ vrndf2.p R020
+ vrndf2.t R010
+ vrndf2.q R100
+ vrndi.s S122
+ vrndi.p R122
+ vrndi.t R112
+ vrndi.q C000
+ vrnds.s S733
+ vs2i.p R700.q, R720.p
+ vs2i.s R700.p, S720.s
+ vsbn.s S123, S321, S433
+ vsbz.s S123, S321
+ vsocp.p R000.q, R000.p
+ vsocp.s R000.p, S000.s
+ vsrt1.q R000, C000
+ vsrt2.q R000, C000
+ vsrt3.q R000, C000
+ vsrt4.q R000, C000
+ vuc2ifs.s R700.q, S723
+ vus2i.p R700.q, R720.p
+ vus2i.s R700.p, S720.s
+ vwbn.s S123, S321, 155
+
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index e21096cfc0b..0d1b4b9377e 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -174,6 +174,9 @@ enum mips_operand_type {
/* A VFPU register prefix. */
OP_VFPU_PFX,
+ /* A VFPU constant/immediate. */
+ OP_VFPU_IMM,
+
/* An index selected by an integer, e.g. [1]. */
OP_IMM_INDEX,
@@ -252,6 +255,12 @@ enum mips_vfpu_reg_type {
OP_VFPU_REG_D
};
+/* Enumerates the types of VFPU immediates. */
+enum mips_vfpu_imm_type {
+ /* Half-float immediate (16 bit half-precision float). */
+ OP_VFPU_FP16
+};
+
/* Enumerates the types of VFPU register-prefix compatibility. */
enum mips_vfpu_regpfx_compat {
/* All prefixes are allowed. */
@@ -433,6 +442,17 @@ struct mips_vfpu_reg_operand
enum mips_vfpu_regdst_compat regcompat;
};
+/* Describes a VFPU immediate, which can encode a variety of things, from
+ simple immediate values to named constants. */
+struct mips_vfpu_imm_operand
+{
+ /* Encodes the offset. */
+ struct mips_operand root;
+
+ /* Register (sub)type. */
+ enum mips_vfpu_imm_type immtype;
+};
+
/* Return true if the assembly syntax allows OPERAND to be omitted. */
static inline bool
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 0252f23d130..6e9c5d18e30 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -27,6 +27,7 @@
#include "elf-bfd.h"
#include "elf/mips.h"
#include "elfxx-mips.h"
+#include <math.h>
/* FIXME: These are needed to figure out if the code is mips16 or
not. The low bit of the address is often a good indicator. No
@@ -1463,6 +1464,42 @@ print_vfpu_pfx (struct disassemble_info *info,
}
+/* Print OP_VFPU_IMM operand OPERAND, whose value is given by UVAL. */
+static void
+print_vfpu_imm (struct disassemble_info *info,
+ const struct mips_vfpu_imm_operand *operand, unsigned int uval)
+{
+ const fprintf_styled_ftype infprintf = info->fprintf_styled_func;
+ void *is = info->stream;
+
+ switch (operand->immtype)
+ {
+ case OP_VFPU_FP16:
+ {
+ /* Prints a float16 making sure to cover all corner cases. */
+ int sign = (uval >> 15) & 1;
+ int expo = (uval >> 10) & 0x1f;
+ int mant = uval & 0x3ff;
+
+ if (expo == 0x1f)
+ {
+ float f = mant ? NAN : INFINITY;
+ infprintf (is, dis_style_immediate, "%g", sign ? -f : f);
+ }
+ else if (!expo && !mant)
+ infprintf (is, dis_style_immediate, sign ? "-0" : "+0");
+ else
+ {
+ float f = mant | (expo ? 0x400 : 0);
+ f = ldexpf(f, expo - 15 - 10);
+ infprintf (is, dis_style_immediate, "%g", sign ? -f : f);
+ }
+ }
+ break;
+ }
+}
+
+
/* Record information about a register operand. */
static void
@@ -1680,6 +1717,10 @@ print_insn_arg (struct disassemble_info *info,
print_vfpu_pfx (info, operand, uval);
break;
+ case OP_VFPU_IMM:
+ print_vfpu_imm (info, (struct mips_vfpu_imm_operand*)operand, uval);
+ break;
+
case OP_PERF_REG:
infprintf (is, dis_style_register, "%d", uval);
break;
@@ -2021,6 +2062,7 @@ validate_insn_args (const struct mips_opcode *opcode,
case OP_SAVE_RESTORE_LIST:
case OP_VFPU_REG:
case OP_VFPU_PFX:
+ case OP_VFPU_IMM:
break;
}
}
diff --git a/opcodes/mips-formats.h b/opcodes/mips-formats.h
index 53e8698e933..e0840611216 100644
--- a/opcodes/mips-formats.h
+++ b/opcodes/mips-formats.h
@@ -157,6 +157,14 @@
#define VFPU_PFX(SIZE, LSB, RTYPE, RSIZE) \
VFPU_REGEXP(PFX, SIZE, LSB, RTYPE, false, RSIZE, ALL, ALL)
+#define VFPU_IMM(SIZE, LSB, SUBTYPE) \
+ { \
+ static const struct mips_vfpu_imm_operand op = { \
+ { OP_VFPU_IMM, SIZE, LSB }, OP_VFPU_##SUBTYPE, \
+ }; \
+ return &op.root; \
+ }
+
#define PCREL(SIZE, LSB, IS_SIGNED, SHIFT, ALIGN_LOG2, INCLUDE_ISA_BIT, \
FLIP_ISA_BIT) \
{ \
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 0a82435c955..ab45735e20c 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -160,6 +160,15 @@ decode_mips_operand (const char *p)
default:
abort();
}
+ case 'j':
+ switch (p[2])
+ {
+ case 'f': VFPU_IMM(16, 0, FP16);
+ case 's': UINT(5, 16);
+ case 'e': HINT(8, 16);
+ default:
+ abort();
+ }
default:
abort();
}
@@ -694,6 +703,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"vnop", "", 0xffff0000, 0xffffffff, CP, 0, ALX, 0, 0 },
/* Allegrex VFPU coprocessor. Redefines coprocessor 2 and 3 (and other unused opcodes). */
+{"mfv", "t,?d0n", 0x48600000, 0xffe0ff80, WR_1|RD_C2, 0, ALX, 0, 0 },
+{"mtv", "t,?d0n", 0x48e00000, 0xffe0ff80, RD_1|WR_C2, 0, ALX, 0, 0 },
{"vabs.p", "?d1a,?s1l", 0xd0010080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vabs.q", "?d3a,?s3l", 0xd0018080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vabs.s", "?d0a,?s0l", 0xd0010000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
@@ -709,12 +720,17 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"vavg.p", "?d0a,?s1a", 0xd0470080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vavg.q", "?d0a,?s3a", 0xd0478080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vavg.t", "?d0a,?s2a", 0xd0478000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vbfy1.p", "?d1a,?s1n", 0xd0420080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vbfy1.q", "?d3a,?s3n", 0xd0428080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vbfy2.q", "?d3a,?s3n", 0xd0438080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vc2i.s", "?d3l,?s0n", 0xd0390000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vcos.p", "?D1n,?s1n", 0xd0130080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vcos.q", "?D3n,?s3n", 0xd0138080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vcos.s", "?D0n,?s0n", 0xd0130000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vcos.t", "?D2n,?s2n", 0xd0138000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vcrsp.t", "?i2n,?s2n,?t2n", 0xf2808000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vcrs.t", "?d2a,?s2n,?t2n", 0x66808000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vdet.p", "?d0a,?s1a,?t1n", 0x67000080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vdiv.p", "?D1n,?s1n,?t1n", 0x63800080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vdiv.q", "?D3n,?s3n,?t3n", 0x63808080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vdiv.s", "?D0n,?s0n,?t0n", 0x63800000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
@@ -726,17 +742,51 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"vexp2.q", "?D3n,?s3n", 0xd0148080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vexp2.s", "?D0n,?s0n", 0xd0140000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vexp2.t", "?D2n,?s2n", 0xd0148000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vf2h.p", "?d0l,?s1a", 0xd0320080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vf2h.q", "?d1l,?s3a", 0xd0328080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vf2id.p", "?d1l,?s1a,?js.", 0xd2600080, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vf2id.q", "?d3l,?s3a,?js.", 0xd2608080, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vf2id.s", "?d0l,?s0a,?js.", 0xd2600000, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vf2id.t", "?d2l,?s2a,?js.", 0xd2608000, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vf2in.p", "?d1l,?s1a,?js.", 0xd2000080, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vf2in.q", "?d3l,?s3a,?js.", 0xd2008080, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vf2in.s", "?d0l,?s0a,?js.", 0xd2000000, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vf2in.t", "?d2l,?s2a,?js.", 0xd2008000, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vf2iu.p", "?d1l,?s1a,?js.", 0xd2400080, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vf2iu.q", "?d3l,?s3a,?js.", 0xd2408080, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vf2iu.s", "?d0l,?s0a,?js.", 0xd2400000, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vf2iu.t", "?d2l,?s2a,?js.", 0xd2408000, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vf2iz.p", "?d1l,?s1a,?js.", 0xd2200080, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vf2iz.q", "?d3l,?s3a,?js.", 0xd2208080, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vf2iz.s", "?d0l,?s0a,?js.", 0xd2200000, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vf2iz.t", "?d2l,?s2a,?js.", 0xd2208000, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vfad.p", "?d0a,?s1a", 0xd0460080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vfad.q", "?d0a,?s3a", 0xd0468080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vfad.t", "?d0a,?s2a", 0xd0468000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vfim.s", "?t0a,?jf.", 0xdf800000, 0xff800000, WR_C2, 0, ALX, 0, 0 },
{"vflush", "", 0xffff040d, 0xffffffff, CP, 0, ALX, 0, 0 },
+{"vh2f.p", "?d3a,?s1n", 0xd0330080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vh2f.s", "?d1a,?s0n", 0xd0330000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vhdp.p", "?d0a,?s1n,?t1a", 0x66000080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vhdp.q", "?d0a,?s3n,?t3a", 0x66008080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vhdp.t", "?d0a,?s2n,?t2a", 0x66008000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vhtfm2.p", "?i1n,?s4n,?t1n", 0xf0800000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vhtfm3.t", "?i2n,?s5n,?t2n", 0xf1000080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vhtfm4.q", "?i3n,?s6n,?t3n", 0xf1808000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vi2c.q", "?d1l,?s3l", 0xd03d8080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vi2f.p", "?d1a,?s1l,?js.", 0xd2800080, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vi2f.q", "?d3a,?s3l,?js.", 0xd2808080, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vi2f.s", "?d0a,?s0l,?js.", 0xd2800000, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vi2f.t", "?d2a,?s2l,?js.", 0xd2808000, 0xffe08080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vi2s.p", "?d0l,?s1l", 0xd03f0080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vi2s.q", "?d1l,?s3l", 0xd03f8080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vi2uc.q", "?d1l,?s3l", 0xd03c8080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vi2us.p", "?d0l,?s1l", 0xd03e0080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vi2us.q", "?d1l,?s3l", 0xd03e8080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vidt.p", "?d1a", 0xd0030080, 0xffffff80, WR_C2, 0, ALX, 0, 0 },
{"vidt.q", "?d3a", 0xd0038080, 0xffffff80, WR_C2, 0, ALX, 0, 0 },
+{"viim.s", "?t0a,j", 0xdf000000, 0xff800000, WR_C2, 0, ALX, 0, 0 },
+{"vlgb.s", "?d0a,?s0a", 0xd0370000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vlog2.p", "?D1n,?s1n", 0xd0150080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vlog2.q", "?D3n,?s3n", 0xd0158080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vlog2.s", "?D0n,?s0n", 0xd0150000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
@@ -807,10 +857,25 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"vrexp2.q", "?D3n,?s3n", 0xd01c8080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vrexp2.s", "?D0n,?s0n", 0xd01c0000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vrexp2.t", "?D2n,?s2n", 0xd01c8000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vrndf1.p", "?d1n", 0xd0220080, 0xffffff80, WR_C2, 0, ALX, 0, 0 },
+{"vrndf1.q", "?d3n", 0xd0228080, 0xffffff80, WR_C2, 0, ALX, 0, 0 },
+{"vrndf1.s", "?d0n", 0xd0220000, 0xffffff80, WR_C2, 0, ALX, 0, 0 },
+{"vrndf1.t", "?d2n", 0xd0228000, 0xffffff80, WR_C2, 0, ALX, 0, 0 },
+{"vrndf2.p", "?d1n", 0xd0230080, 0xffffff80, WR_C2, 0, ALX, 0, 0 },
+{"vrndf2.q", "?d3n", 0xd0238080, 0xffffff80, WR_C2, 0, ALX, 0, 0 },
+{"vrndf2.s", "?d0n", 0xd0230000, 0xffffff80, WR_C2, 0, ALX, 0, 0 },
+{"vrndf2.t", "?d2n", 0xd0238000, 0xffffff80, WR_C2, 0, ALX, 0, 0 },
+{"vrndi.p", "?d1n", 0xd0210080, 0xffffff80, WR_C2, 0, ALX, 0, 0 },
+{"vrndi.q", "?d3n", 0xd0218080, 0xffffff80, WR_C2, 0, ALX, 0, 0 },
+{"vrndi.s", "?d0n", 0xd0210000, 0xffffff80, WR_C2, 0, ALX, 0, 0 },
+{"vrndi.t", "?d2n", 0xd0218000, 0xffffff80, WR_C2, 0, ALX, 0, 0 },
+{"vrnds.s", "?s0n", 0xd0200000, 0xffff80ff, WR_C2, 0, ALX, 0, 0 },
{"vrsq.p", "?D1n,?s1n", 0xd0110080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vrsq.q", "?D3n,?s3n", 0xd0118080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vrsq.s", "?D0n,?s0n", 0xd0110000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vrsq.t", "?D2n,?s2n", 0xd0118000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vs2i.p", "?d3l,?s1n", 0xd03b0080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vs2i.s", "?d1l,?s0n", 0xd03b0000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vsat0.p", "?d1n,?s1a", 0xd0040080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vsat0.q", "?d3n,?s3a", 0xd0048080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vsat0.s", "?d0n,?s0a", 0xd0040000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
@@ -819,6 +884,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"vsat1.q", "?d3n,?s3a", 0xd0058080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vsat1.s", "?d0n,?s0a", 0xd0050000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vsat1.t", "?d2n,?s2a", 0xd0058000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vsbn.s", "?d0a,?s0a,?t0a", 0x61000000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vsbz.s", "?d0a,?s0a", 0xd0360000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vscl.p", "?d1a,?s1a,?t0n", 0x65000080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vscl.q", "?d3a,?s3a,?t0n", 0x65008080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vscl.t", "?d2a,?s2a,?t0n", 0x65008000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
@@ -842,10 +909,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"vslt.q", "?d3a,?s3a,?t3a", 0x6f808080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vslt.s", "?d0a,?s0a,?t0a", 0x6f800000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vslt.t", "?d2a,?s2a,?t2a", 0x6f808000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vsocp.p", "?d3n,?s1n", 0xd0450080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vsocp.s", "?d1n,?s0n", 0xd0450000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vsqrt.p", "?D1n,?s1n", 0xd0160080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vsqrt.q", "?D3n,?s3n", 0xd0168080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vsqrt.s", "?D0n,?s0n", 0xd0160000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vsqrt.t", "?D2n,?s2n", 0xd0168000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vsrt1.q", "?d3a,?s3n", 0xd0408080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vsrt2.q", "?d3a,?s3n", 0xd0418080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vsrt3.q", "?d3a,?s3n", 0xd0488080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vsrt4.q", "?d3a,?s3n", 0xd0498080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vsub.p", "?d1a,?s1a,?t1a", 0x60800080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vsub.q", "?d3a,?s3a,?t3a", 0x60808080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vsub.s", "?d0a,?s0a,?t0a", 0x60800000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
@@ -858,6 +931,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"vtfm2.p", "?i1n,?s4n,?t1n", 0xf0800080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vtfm3.t", "?i2n,?s5n,?t2n", 0xf1008000, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vtfm4.q", "?i3n,?s6n,?t3n", 0xf1808080, 0xff808080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vuc2ifs.s", "?d3l,?s0n", 0xd0380000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vus2i.p", "?d3l,?s1n", 0xd03a0080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vus2i.s", "?d1l,?s0n", 0xd03a0000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vwbn.s", "?d0a,?s0a,?je.", 0xd3000000, 0xff008080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vzero.p", "?d1a", 0xd0060080, 0xffffff80, WR_C2, 0, ALX, 0, 0 },
{"vzero.q", "?d3a", 0xd0068080, 0xffffff80, WR_C2, 0, ALX, 0, 0 },
{"vzero.s", "?d0a", 0xd0060000, 0xffffff80, WR_C2, 0, ALX, 0, 0 },
--
2.51.1
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