[PATCH] RISC-V: Align vconfig for TARGER_SFB_ALU

[Dusan Stojkovic]

  This patch addresses a missed opportunity to fuse vsetvl_infos.
Instead of checking whether demands for merging configurations of
vsetvl_info are all met, the demands are checked individually.

  The case in question occurs because of the conditional move
instruction which sifive-7, sifive-p400 and sifive-p600 support.
Firstly, the conditional move generated rearranges the CFG.
Secondly, because the conditional move generated uses
the same register in the if_then_else pattern as vsetvli before it
curr_info and prev_info won't be merged.

  Tested for tune={sifive-7-series, sifive-p400-series, sifive-p600-series}
and arch={rv64gcv, rv32gcv} making no new regressions.
The fusion performed also makes the following tests pass:
* vsetvlmax-9.c
* vsetvlmax-10.c
* vsetvlmax-11.c
* vsetvlmax-15.c
for all tune configurations mentioned. Specifically, the
scan-assembler-times vsetvli\\s+[a-x0-9]+,\\s*zero,\\s*e32,\\s*m1,\\s*t[au],\\s*m[au] 1
tests in previously mentioned files are now passing.

2024-09-10 Dusan Stojkovic <Dusan.Stojkovic@rt-rk.com>

PR target/113035 - RISC-V: regression testsuite errors -mtune=sifive-7-series

        PR target/113035

gcc\ChangeLog:

        * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
---
 gcc/config/riscv/riscv-vsetvl.cc | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 017efa8bc17..f93e0c313b6 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -3052,6 +3052,22 @@ pre_vsetvl::earliest_fuse_vsetvl_info (int iter)
          else
            {
              vsetvl_info &prev_info = src_block_info.get_exit_info ();
+             if (TARGET_SFB_ALU
+             && prev_info.valid_p ()
+             && curr_info.valid_p ()
+             && prev_info.vl_used_by_non_rvv_insn_p ()
+             && !curr_info.vl_used_by_non_rvv_insn_p ())
+             {
+               // Try to merge each demand individually
+               if (m_dem.sew_lmul_compatible_p (prev_info, curr_info))
+               {
+                 m_dem.merge_sew_lmul (prev_info, curr_info);
+               }
+               if (m_dem.policy_compatible_p (prev_info, curr_info))
+               {
+                 m_dem.merge_policy (prev_info, curr_info);
+               }
+             }
              if (!prev_info.valid_p ()
                  || m_dem.available_p (prev_info, curr_info)
                  || !m_dem.compatible_p (prev_info, curr_info))
--
2.43.0

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