[committed] i386: Fix the order of operands in andn<MMXMODEI:mode>3 [PR117192]

[Uros Bizjak]

Fix the order of operands in andn<MMXMODEI:mode>3 expander to comply
with the specification, where bitwise-complement applies to operand 2.

    PR target/117192

gcc/ChangeLog:

    * config/i386/mmx.md (andn<MMXMODEI:mode>3): Swap operand
    indexes 1 and 2 to comply with andn specification.

gcc/testsuite/ChangeLog:

    * gcc.target/i386/pr117192.c: New test.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Uros.
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diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index ef4ed8b501a..506f4cab6a8 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -4470,9 +4470,9 @@ (define_split
 (define_expand "andn<mode>3"
   [(set (match_operand:MMXMODEI 0 "register_operand")
         (and:MMXMODEI
-          (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand"))
-          (match_operand:MMXMODEI 2 "register_operand")))]
-  "TARGET_SSE2")
+          (not:MMXMODEI (match_operand:MMXMODEI 2 "register_operand"))
+          (match_operand:MMXMODEI 1 "register_operand")))]
+  "TARGET_MMX_WITH_SSE")
 
 (define_insn "mmx_andnot<mode>3"
   [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x,v")
diff --git a/gcc/testsuite/gcc.target/i386/pr117192.c b/gcc/testsuite/gcc.target/i386/pr117192.c
new file mode 100644
index 00000000000..8480c72dc0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr117192.c
@@ -0,0 +1,16 @@
+/* PR target/117192 */
+/* { dg-do run } */
+/* { dg-options "-O3 -fno-unswitch-loops" } */
+
+int a, b, c, d;
+int main() {
+  int e[6];
+  for (d = 0; d < 6; d++)
+    if (!c)
+      e[d] = 0;
+  for (; b < 6; b++)
+    a = e[b];
+  if (a != 0)
+    __builtin_abort();
+  return 0;
+}