[PATCH] RISC-V: Implement -m{,no}fence-tso

[Jeff Law]

On 5/14/24 5:13 PM, Palmer Dabbelt wrote:
> Some processors from T-Head don't implement the `fence.tso` instruction
> natively and instead trap to firmware.  This breaks some users who
> haven't yet updated the firmware and one could imagine it breaking users
> who are trying to build firmware if they're using the C memory model.
> 
> So just add an option to disable emitting it, in a similar fashion to
> how we allow users to forbid other instructions.
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/riscv.opt: Add -mno-fence-tso.
> 	* config/riscv/sync-rvwmo.md (mem_thread_fence_rvwmo): Respect
> 	-mno-fence-tso.
> 	* doc/invoke.texi (RISC-V): Document -mno-fence-tso.
> 
> Link: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1070959
> ---
> I've just smoke tested this one, but
> 
>      void func(void) { __atomic_thread_fence(__ATOMIC_ACQ_REL); }
> 
> generates `fence.tso` without the argument and `fence rw,rw` with
> `-mno-fence-tso`, so it seems to be at least mostly there.  I figured
> I'd just send it up for comments before putting together the DG bits:
> it's kind of a pain to carry around these workarounds for unimplemented
> instructions, but it's in HW so there's not much we can do about that.
Seems reasonable.  We might consider adding a comment in the code 
indicating this is for a particular set of thead systems.  10 years from 
now when someone else looks at the code they'll know why this is in 
there and they won't have to do the archaeology.

Jeff