[Committed] RISC-V: Add VLS unary combine patterns

Juzhe-Zhong juzhe.zhong@rivai.ai
Sat Sep 23 01:44:38 GMT 2023


gcc/ChangeLog:

	* config/riscv/autovec-opt.md: Add VLS modes for conditional ABS/SQRT.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c: New test.

---
 gcc/config/riscv/autovec-opt.md               | 30 +++++------
 .../riscv/rvv/autovec/vls/cond_abs-1.c        | 50 +++++++++++++++++++
 .../riscv/rvv/autovec/vls/cond_sqrt-1.c       | 50 +++++++++++++++++++
 3 files changed, 113 insertions(+), 17 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index ed9c0777eb9..6c6609d24bb 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -99,41 +99,37 @@
 ;; Currently supported operations:
 ;;   abs(FP)
 (define_insn_and_split "*cond_abs<mode>"
-  [(set (match_operand:VF 0 "register_operand")
-        (if_then_else:VF
-          (match_operand:<VM> 3 "register_operand")
-          (abs:VF (match_operand:VF 1 "nonmemory_operand"))
-          (match_operand:VF 2 "register_operand")))]
+  [(set (match_operand:V_VLSF 0 "register_operand")
+        (if_then_else:V_VLSF
+          (match_operand:<VM> 1 "register_operand")
+          (abs:V_VLSF (match_operand:V_VLSF 2 "nonmemory_operand"))
+          (match_operand:V_VLSF 3 "register_operand")))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
   "&& 1"
   [(const_int 0)]
 {
-  emit_insn (gen_cond_len_abs<mode> (operands[0], operands[3], operands[1],
-				     operands[2],
-				     gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode),
-				     const0_rtx));
+  insn_code icode = code_for_pred (ABS, <MODE>mode);
+  riscv_vector::expand_cond_unop (icode, operands);
   DONE;
 }
 [(set_attr "type" "vector")])
 
 ;; Combine vfsqrt.v and cond_mask
 (define_insn_and_split "*cond_<optab><mode>"
-  [(set (match_operand:VF 0 "register_operand")
-     (if_then_else:VF
+  [(set (match_operand:V_VLSF 0 "register_operand")
+     (if_then_else:V_VLSF
        (match_operand:<VM> 1 "register_operand")
-       (any_float_unop:VF
-         (match_operand:VF 2 "register_operand"))
-       (match_operand:VF 3 "register_operand")))]
+       (any_float_unop:V_VLSF
+         (match_operand:V_VLSF 2 "register_operand"))
+       (match_operand:V_VLSF 3 "register_operand")))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
   "&& 1"
   [(const_int 0)]
 {
   insn_code icode = code_for_pred (<CODE>, <MODE>mode);
-  rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
-               gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
-  riscv_vector::expand_cond_len_unop (icode, ops);
+  riscv_vector::expand_cond_unop (icode, operands);
   DONE;
 }
 [(set_attr "type" "vector")])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c
new file mode 100644
index 00000000000..3eaabce9611
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_UNOP (cond_abs, 4, v4hf, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 8, v8hf, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 16, v16hf, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 32, v32hf, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 64, v64hf, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 128, v128hf, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 256, v256hf, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 512, v512hf, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 1024, v1024hf, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 2048, v2048hf, __builtin_fabs)
+
+DEF_COND_UNOP (cond_abs, 4, v4sf, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 8, v8sf, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 16, v16sf, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 32, v32sf, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 64, v64sf, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 128, v128sf, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 256, v256sf, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 512, v512sf, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 1024, v1024sf, __builtin_fabs)
+
+DEF_COND_UNOP (cond_abs, 4, v4df, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 8, v8df, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 16, v16df, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 32, v32df, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 64, v64df, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 128, v128df, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 256, v256df, __builtin_fabs)
+DEF_COND_UNOP (cond_abs, 512, v512df, __builtin_fabs)
+
+/* { dg-final { scan-assembler-times {vfabs\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c
new file mode 100644
index 00000000000..1c1c2ab280f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_COND_UNOP (cond_abs, 4, v4hf, __builtin_sqrtf16)
+DEF_COND_UNOP (cond_abs, 8, v8hf, __builtin_sqrtf16)
+DEF_COND_UNOP (cond_abs, 16, v16hf, __builtin_sqrtf16)
+DEF_COND_UNOP (cond_abs, 32, v32hf, __builtin_sqrtf16)
+DEF_COND_UNOP (cond_abs, 64, v64hf, __builtin_sqrtf16)
+DEF_COND_UNOP (cond_abs, 128, v128hf, __builtin_sqrtf16)
+DEF_COND_UNOP (cond_abs, 256, v256hf, __builtin_sqrtf16)
+DEF_COND_UNOP (cond_abs, 512, v512hf, __builtin_sqrtf16)
+DEF_COND_UNOP (cond_abs, 1024, v1024hf, __builtin_sqrtf16)
+DEF_COND_UNOP (cond_abs, 2048, v2048hf, __builtin_sqrtf16)
+
+DEF_COND_UNOP (cond_abs, 4, v4sf, __builtin_sqrtf)
+DEF_COND_UNOP (cond_abs, 8, v8sf, __builtin_sqrtf)
+DEF_COND_UNOP (cond_abs, 16, v16sf, __builtin_sqrtf)
+DEF_COND_UNOP (cond_abs, 32, v32sf, __builtin_sqrtf)
+DEF_COND_UNOP (cond_abs, 64, v64sf, __builtin_sqrtf)
+DEF_COND_UNOP (cond_abs, 128, v128sf, __builtin_sqrtf)
+DEF_COND_UNOP (cond_abs, 256, v256sf, __builtin_sqrtf)
+DEF_COND_UNOP (cond_abs, 512, v512sf, __builtin_sqrtf)
+DEF_COND_UNOP (cond_abs, 1024, v1024sf, __builtin_sqrtf)
+
+DEF_COND_UNOP (cond_abs, 4, v4df, __builtin_sqrt)
+DEF_COND_UNOP (cond_abs, 8, v8df, __builtin_sqrt)
+DEF_COND_UNOP (cond_abs, 16, v16df, __builtin_sqrt)
+DEF_COND_UNOP (cond_abs, 32, v32df, __builtin_sqrt)
+DEF_COND_UNOP (cond_abs, 64, v64df, __builtin_sqrt)
+DEF_COND_UNOP (cond_abs, 128, v128df, __builtin_sqrt)
+DEF_COND_UNOP (cond_abs, 256, v256df, __builtin_sqrt)
+DEF_COND_UNOP (cond_abs, 512, v512df, __builtin_sqrt)
+
+/* { dg-final { scan-assembler-times {vfsqrt\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 27 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-not {vmerge} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
-- 
2.36.3



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