[PATCH] RISC-V: Fixed ICE caused by missing operand

Lehua Ding lehua.ding@rivai.ai
Wed Sep 20 05:39:54 GMT 2023


This ICE appears in GCC compiled with -O2 flags.

	PR target/111488

gcc/ChangeLog:

	* config/riscv/autovec-opt.md: Add missed operand.

---
 gcc/config/riscv/autovec-opt.md | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index cef9f157e99..66c77ad6ebb 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -957,7 +957,8 @@
     riscv_vector::emit_vlmax_insn (extend_icode, riscv_vector::UNARY_OP,
                                    extend_ops);

-    rtx ops[] = {operands[0], tmp, operands[3], operands[1]};
+    rtx ops[] = {operands[0], tmp, operands[3], operands[1],
+                 RVV_VUNDEF(<MODE>mode)};
     riscv_vector::emit_vlmax_insn (code_for_pred_mul_plus (<MODE>mode),
 				   riscv_vector::TERNARY_OP, ops);
     DONE;
@@ -1008,7 +1009,8 @@
     rtx ext_ops[] = {tmp, operands[2]};
     riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ext_ops);

-    rtx ops[] = {operands[0], tmp, operands[3], operands[1]};
+    rtx ops[] = {operands[0], tmp, operands[3], operands[1],
+                 RVV_VUNDEF(<MODE>mode)};
     riscv_vector::emit_vlmax_insn (code_for_pred_mul (PLUS, <MODE>mode),
 				   riscv_vector::TERNARY_OP_FRM_DYN, ops);
     DONE;
@@ -1059,7 +1061,8 @@
     rtx ext_ops[] = {tmp, operands[2]};
     riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ext_ops);

-    rtx ops[] = {operands[0], tmp, operands[3], operands[1]};
+    rtx ops[] = {operands[0], tmp, operands[3], operands[1],
+                 RVV_VUNDEF(<MODE>mode)};
     riscv_vector::emit_vlmax_insn (code_for_pred_mul_neg (PLUS, <MODE>mode),
 				   riscv_vector::TERNARY_OP_FRM_DYN, ops);
     DONE;
@@ -1110,7 +1113,8 @@
     rtx ext_ops[] = {tmp, operands[2]};
     riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ext_ops);

-    rtx ops[] = {operands[0], tmp, operands[3], operands[1]};
+    rtx ops[] = {operands[0], tmp, operands[3], operands[1],
+                 RVV_VUNDEF(<MODE>mode)};
     riscv_vector::emit_vlmax_insn (code_for_pred_mul (MINUS, <MODE>mode),
 				   riscv_vector::TERNARY_OP_FRM_DYN, ops);
     DONE;
@@ -1163,7 +1167,8 @@
     rtx ext_ops[] = {tmp, operands[2]};
     riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ext_ops);

-    rtx ops[] = {operands[0], tmp, operands[3], operands[1]};
+    rtx ops[] = {operands[0], tmp, operands[3], operands[1],
+                 RVV_VUNDEF(<MODE>mode)};
     riscv_vector::emit_vlmax_insn (code_for_pred_mul_neg (MINUS, <MODE>mode),
 				   riscv_vector::TERNARY_OP_FRM_DYN, ops);
     DONE;
--
2.36.3



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