[PATCH] RISC-V: Add VLS modes VEC_PERM support[PR111311]

juzhe.zhong@rivai.ai juzhe.zhong@rivai.ai
Mon Sep 11 03:24:51 GMT 2023


Sure. Thanks kito.



juzhe.zhong@rivai.ai
 
From: Kito Cheng
Date: 2023-09-11 10:57
To: juzhe.zhong@rivai.ai
CC: gcc-patches; Kito.cheng
Subject: Re: Re: [PATCH] RISC-V: Add VLS modes VEC_PERM support[PR111311]
OK, but could you split this patch into two patches? pre-approved for both.
 
On Mon, Sep 11, 2023 at 10:36 AM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> >> Should we also add loads and stores as well?
> >> and just make sure this is also necessary for the fix and not sneaky, right?
>
> No, we don't need loads/stores. Since this following handling codes:
> (define_insn_and_split "*mov<VLS_AVL_REG:mode><P:mode>_lra"
>   [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=vr, m,vr")
>   (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" "  m,vr,vr"))
>    (clobber (match_scratch:P 2 "=&r,&r,X"))]
>   "TARGET_VECTOR && (lra_in_progress || reload_completed)
>    && (register_operand (operands[0], <VLS_AVL_REG:MODE>mode)
>        || register_operand (operands[1], <VLS_AVL_REG:MODE>mode))"
>   "#"
>   "&& reload_completed"
>   [(const_int 0)]
> {
>   if (REG_P (operands[0]) && REG_P (operands[1]))
>       emit_insn (gen_rtx_SET (operands[0], operands[1]));
>   else
>     {
>       emit_move_insn (operands[2], gen_int_mode (GET_MODE_NUNITS (<VLS_AVL_REG:MODE>mode),
>              Pmode));
>       unsigned insn_flags
>         = GET_MODE_CLASS (<VLS_AVL_REG:MODE>mode) == MODE_VECTOR_BOOL
>                  ? riscv_vector::UNARY_MASK_OP
>                  : riscv_vector::UNARY_OP;
>       riscv_vector::emit_nonvlmax_insn (code_for_pred_mov (<VLS_AVL_REG:MODE>mode),
>           insn_flags, operands, operands[2]);
>     }
>   DONE;
> }
>   [(set_attr "type" "vmov")]
> )
>
> We split special case use emit_insn (gen_rtx_SET (operands[0], operands[1]));
>
> Missing this pattern will cause ICE but current testcases didn't produce such issues.
> This issue is recognized after I support this pattern.
>
>
>
> juzhe.zhong@rivai.ai
>
> From: Kito Cheng
> Date: 2023-09-11 10:18
> To: Juzhe-Zhong
> CC: gcc-patches; kito.cheng
> Subject: Re: [PATCH] RISC-V: Add VLS modes VEC_PERM support[PR111311]
> > diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
> > index d208b418e5f..6f48f7d6232 100644
> > --- a/gcc/config/riscv/autovec-vls.md
> > +++ b/gcc/config/riscv/autovec-vls.md
> > @@ -148,6 +148,14 @@
> >    [(set_attr "type" "vmov")
> >     (set_attr "mode" "<MODE>")])
> >
> > +(define_insn "*mov<mode>_vls"
> > +  [(set (match_operand:VLSB 0 "register_operand" "=vr")
> > +       (match_operand:VLSB 1 "register_operand" " vr"))]
> > +  "TARGET_VECTOR"
> > +  "vmv1r.v\t%0,%1"
> > +  [(set_attr "type" "vmov")
> > +   (set_attr "mode" "<MODE>")])
>
> Should we also add loads and stores as well?
> and just make sure this is also necessary for the fix and not sneaky, right?
>
> > +
> >  (define_expand "movmisalign<mode>"
> >    [(set (match_operand:VLS 0 "nonimmediate_operand")
> >         (match_operand:VLS 1 "general_operand"))]
>
 


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