[PATCH] RISC-V: Avoid unnecessary slideup in compress pattern of vec_perm

Juzhe-Zhong juzhe.zhong@rivai.ai
Sun Sep 10 03:55:38 GMT 2023


If a const vector all elements are same, the slide up is unnecessary.

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (shuffle_compress_patterns): Avoid unnecessary slideup.

---
 gcc/config/riscv/riscv-v.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index bee60de1d26..7ef884907b8 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2697,7 +2697,7 @@ shuffle_compress_patterns (struct expand_vec_perm_d *d)
   rtx mask = force_reg (mask_mode, builder.build ());
 
   rtx merge = d->op1;
-  if (need_slideup_p)
+  if (need_slideup_p && !const_vec_duplicate_p (d->op1))
     {
       int slideup_cnt = vlen - (d->perm[vlen - 1].to_constant () % vlen) - 1;
       rtx ops[] = {d->target, d->op1, gen_int_mode (slideup_cnt, Pmode)};
-- 
2.36.3



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