[PATCH 1/5] aarch64: rcpc3: Add +rcpc3 extension

[Richard Sandiford]

Victor Do Nascimento <victor.donascimento@arm.com> writes:
> Given the optional LRCPC3 target support for Armv8.2-a cores onwards,
> the +rcpc3 arch feature modifier is added to GCC's command-line options.
>
> gcc/ChangeLog:
>
> 	* config/aarch64/aarch64-option-extensions.def (rcpc3): New.
> 	* config/aarch64/aarch64.h (AARCH64_ISA_RCPC3): Likewise.
> 	(TARGET_RCPC3): Likewise.
> 	* doc/invoke.texi (rcpc3): Document feature in AArch64 Options.
> ---
>  gcc/config/aarch64/aarch64-option-extensions.def | 1 +
>  gcc/config/aarch64/aarch64.h                     | 4 ++++
>  gcc/doc/invoke.texi                              | 4 ++++
>  3 files changed, 9 insertions(+)
>
> diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
> index 825f3bf7758..2ab94799d34 100644
> --- a/gcc/config/aarch64/aarch64-option-extensions.def
> +++ b/gcc/config/aarch64/aarch64-option-extensions.def
> @@ -151,4 +151,5 @@ AARCH64_OPT_EXTENSION("mops", MOPS, (), (), (), "")
>  
>  AARCH64_OPT_EXTENSION("cssc", CSSC, (), (), (), "cssc")
>  
> +AARCH64_OPT_EXTENSION("rcpc3", RCPC3, (), (), (), "rcpc3")
>  #undef AARCH64_OPT_EXTENSION
> diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
> index 2f0777a37ac..68bbaccef1a 100644
> --- a/gcc/config/aarch64/aarch64.h
> +++ b/gcc/config/aarch64/aarch64.h
> @@ -213,6 +213,7 @@ enum class aarch64_feature : unsigned char {
>  #define AARCH64_ISA_F64MM	   (aarch64_isa_flags & AARCH64_FL_F64MM)
>  #define AARCH64_ISA_BF16	   (aarch64_isa_flags & AARCH64_FL_BF16)
>  #define AARCH64_ISA_SB		   (aarch64_isa_flags & AARCH64_FL_SB)
> +#define AARCH64_ISA_RCPC3	   (aarch64_isa_flags & AARCH64_FL_RCPC3)
>  #define AARCH64_ISA_V8R		   (aarch64_isa_flags & AARCH64_FL_V8R)
>  #define AARCH64_ISA_PAUTH	   (aarch64_isa_flags & AARCH64_FL_PAUTH)
>  #define AARCH64_ISA_V9A		   (aarch64_isa_flags & AARCH64_FL_V9A)
> @@ -344,6 +345,9 @@ enum class aarch64_feature : unsigned char {
>     and sign-extending versions.*/
>  #define TARGET_RCPC2 (AARCH64_ISA_RCPC8_4)
>  
> +/* RCPC3 LDAP1/STL1 loads/stores from Armv8.2-a.  */
> +#define TARGET_RCPC3 (AARCH64_ISA_RCPC3)

The extension is more general than that, so maybe just:

/* RCPC3 (Release Consistency) extensions, optional from Armv8.2-A.  */

> +
>  /* Apply the workaround for Cortex-A53 erratum 835769.  */
>  #define TARGET_FIX_ERR_A53_835769	\
>    ((aarch64_fix_a53_err835769 == 2)	\
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 6e776a0faa1..ba28eb195ce 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -21028,6 +21028,10 @@ Enable the Flag Manipulation instructions Extension.
>  Enable the Pointer Authentication Extension.
>  @item cssc
>  Enable the Common Short Sequence Compression instructions.
> +@item rcpc3
> +Enable the RCpc3 extension.  This enables the use of the LDAP1 and
> +STL1 instructions for loads/stores of 64-bit values to and from SIMD
> +register lanes, passing these on to the assembler.

Similarly here, it's probably enough to say:

Enable the RCpc3 (Release Consistency) extension.

OK with those changes, thanks.

Richard