[PATCH] RISC-V: Remove FRM for vfncvt.rod instruction

[Li, Pan2]

Committed, thanks Jeff.

Pan

-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Jeff Law via Gcc-patches
Sent: Wednesday, May 31, 2023 9:02 PM
To: juzhe.zhong@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com; kito.cheng@sifive.com; palmer@dabbelt.com; palmer@rivosinc.com; rdapp.gcc@gmail.com
Subject: Re: [PATCH] RISC-V: Remove FRM for vfncvt.rod instruction



On 5/31/23 04:47, juzhe.zhong@rivai.ai wrote:
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
> 
> Apparently, vfncvt.rod rounding mode is encoded, so we don't need FRM.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/vector.md: Remove FRM.
OK
jeff