[PATCH] RISC-V: Reorganize the code of CONST_VECTOR handling in riscv.cc

[Kito Cheng]

LGTM

On Mon, May 22, 2023 at 3:20 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> Since satisfies_constraint_vi (x) belongs to RVV region.
> We make this condition inside riscv_v_ext_vector_mode_p to make codes
> more reasonable.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.cc (riscv_const_insns): Reorganize the codes.
>
> ---
>  gcc/config/riscv/riscv.cc | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 7bb38978261..5ac187c1b1b 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -1295,13 +1295,13 @@ riscv_const_insns (rtx x)
>                  * accurately according to BASE && STEP.  */
>                 return 1;
>               }
> +           /* Constants from -16 to 15 can be loaded with vmv.v.i.
> +              The Wc0, Wc1 constraints are already covered by the
> +              vi constraint so we do not need to check them here
> +              separately.  */
> +           if (satisfies_constraint_vi (x))
> +             return 1;
>           }
> -       /* Constants from -16 to 15 can be loaded with vmv.v.i.
> -          The Wc0, Wc1 constraints are already covered by the
> -          vi constraint so we do not need to check them here
> -          separately.  */
> -       if (TARGET_VECTOR && satisfies_constraint_vi (x))
> -         return 1;
>
>         /* TODO: We may support more const vector in the future.  */
>         return x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
> --
> 2.36.3
>