[PATCH] RISC-V: Call DCE to remove redundant instructions created by the PASS

juzhe.zhong@rivai.ai juzhe.zhong@rivai.ai
Mon Jan 9 23:20:57 GMT 2023


From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

        * config/riscv/riscv-vsetvl.cc (pass_vsetvl::done): Add DCE.
        * config/riscv/t-riscv: Add DCE.

---
 gcc/config/riscv/riscv-vsetvl.cc | 2 ++
 gcc/config/riscv/t-riscv         | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 7d8c3a32aaa..7aa2852b456 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -87,6 +87,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "predict.h"
 #include "profile-count.h"
 #include "riscv-vsetvl.h"
+#include "dce.h"
 
 using namespace rtl_ssa;
 using namespace riscv_vector;
@@ -2627,6 +2628,7 @@ pass_vsetvl::done (void)
 	cleanup_cfg (0);
       delete crtl->ssa;
       crtl->ssa = nullptr;
+      run_fast_dce ();
     }
   m_vector_manager->release ();
   delete m_vector_manager;
diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
index d30e0235356..c95f4aff358 100644
--- a/gcc/config/riscv/t-riscv
+++ b/gcc/config/riscv/t-riscv
@@ -54,7 +54,7 @@ riscv-c.o: $(srcdir)/config/riscv/riscv-c.cc $(CONFIG_H) $(SYSTEM_H) \
 riscv-vsetvl.o: $(srcdir)/config/riscv/riscv-vsetvl.cc \
   $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) $(REGS_H) \
   $(TARGET_H) tree-pass.h df.h rtl-ssa.h cfgcleanup.h insn-config.h \
-  insn-attr.h insn-opinit.h tm-constrs.h cfgrtl.h cfganal.h lcm.h \
+  insn-attr.h insn-opinit.h tm-constrs.h cfgrtl.h cfganal.h lcm.h dce.h \
   predict.h profile-count.h $(srcdir)/config/riscv/riscv-vsetvl.h
 	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
 		$(srcdir)/config/riscv/riscv-vsetvl.cc
-- 
2.36.1



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