[PATCH] aarch64: allow ld1/stq in test output [PR102517]

Richard Earnshaw rearnsha@arm.com
Thu Jan 20 15:45:28 GMT 2022

Following the changes to the inline memcpy operations get expanded, we
now generate ld1/st1 using a 128-bit vector register rather than ldp
with Q registers.  The behaviour is equivalent, so relax the tests to
permit either variant.


	PR target/102517
	* gcc.target/aarch64/cpymem-q-reg_1.c: Allow ld1 and st1 for the
	memcpy expansion.
 gcc/testsuite/gcc.target/aarch64/cpymem-q-reg_1.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

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