[PATCH] i386: Add 16-bit vector modes to xop_pcmov [PR104003]
Uros Bizjak
ubizjak@gmail.com
Thu Jan 13 16:25:29 GMT 2022
2022-01-13 Uroš Bizjak <ubizjak@gmail.com>
gcc/ChangeLog:
PR target/104003
* config/i386/mmx.md (*xop_pcmov_<mode>): Use VI_16_32 mode iterator.
gcc/testsuite/ChangeLog:
PR target/104003
* g++.target/i386/pr103861-1-sse4.C: New test.
* g++.target/i386/pr103861-1-xop.C: Ditto.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Pushed to master.
Uros.
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diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 8a8142c8a09..295a132bc46 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -2704,11 +2704,11 @@
[(set_attr "type" "sse4arg")])
(define_insn "*xop_pcmov_<mode>"
- [(set (match_operand:VI_32 0 "register_operand" "=x")
- (if_then_else:VI_32
- (match_operand:VI_32 3 "register_operand" "x")
- (match_operand:VI_32 1 "register_operand" "x")
- (match_operand:VI_32 2 "register_operand" "x")))]
+ [(set (match_operand:VI_16_32 0 "register_operand" "=x")
+ (if_then_else:VI_16_32
+ (match_operand:VI_16_32 3 "register_operand" "x")
+ (match_operand:VI_16_32 1 "register_operand" "x")
+ (match_operand:VI_16_32 2 "register_operand" "x")))]
"TARGET_XOP"
"vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "sse4arg")])
diff --git a/gcc/testsuite/g++.target/i386/pr103861-1-sse4.C b/gcc/testsuite/g++.target/i386/pr103861-1-sse4.C
new file mode 100644
index 00000000000..a07b3ad111d
--- /dev/null
+++ b/gcc/testsuite/g++.target/i386/pr103861-1-sse4.C
@@ -0,0 +1,5 @@
+/* PR target/103861 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse4" } */
+
+#include "pr103861-1.C"
diff --git a/gcc/testsuite/g++.target/i386/pr103861-1-xop.C b/gcc/testsuite/g++.target/i386/pr103861-1-xop.C
new file mode 100644
index 00000000000..d65542dc57f
--- /dev/null
+++ b/gcc/testsuite/g++.target/i386/pr103861-1-xop.C
@@ -0,0 +1,5 @@
+/* PR target/103861 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mxop" } */
+
+#include "pr103861-1.C"
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