[PATCH] Improve converting between 128-bit modes that use the same format

Michael Meissner meissner@linux.ibm.com
Thu Aug 18 21:48:29 GMT 2022


mprove converting between 128-bit modes that use the same format.

This patch improves the insns used for converting between two modes using
the 128-bit floating point format (i.e. converting between KFmode and TFmode if
-mabi=ieeelongdouble is used, and converting between IFmode and TFmode if
-mabi=ibmlongdouble is used).  The new insns have the correct insn type and
instruction length for the move involved.

Previously, the two different moves were lumped together (i.e. converting
between IEEE 128-bit and IEEE 128-bit was matched by the same insns as
converting between IBM 128-bit and IBM 128-bit moves).

I have tested this patch on the following systems:

    1)	LE Power10 using --with-cpu=power10 --with-long-double-format=ieee
    2)	LE Power10 using --with-cpu=power9  --with-long-double-format=ibm
    3)	LE Power10 using --with-cpu=power8  --with-long-double-format=ibm
    4)	LE Power10 using --with-cpu=power10 --with-long-double-format=ibm
    5)	LE Power9  using --with-cpu=power9  --with-long-double-format=ibm
    6)	BE Power8  using --with-cpu=power8  --with-long-double-format=ibm
    7)	BE Power8  using --with-cpu=power5  --with-long-double-format=ibm

There were no regressions in the build or in the tests.  On the power10 with
long double using the IEEE 128-bit format, pr105334.c now runs where it
previously failed.

Can I check this patch into the trunk?

Did we want to backport this to earlier GCC releases?

2022-08-17   Michael Meissner  <meissner@linux.ibm.com>

gcc/

	* config/rs6000/rs6000.md (IFKF): Delete.
	(IFKF_reg): Delete.
	(extendkfif2): New define_expand.
	(trunckfif2): New define_expand.
	(extend<mode>tf2_internal): Split into extendiftf2_internal and
	extendkftf2_internal.  Update the insns to use the correct insn type and
	length attributes based on whether the move uses IEEE 128-bit floating
	point or IBM 128-bit floating point type.
	(extendiftf2_internal): Likewise.
	(extendkftf2_internal): Likewise.
	(extendtf<mode>2_internal): Split into extendtfif2_internal and
	extendtfkf2_internal.  Update the insns to use the correct insn type and
	length attributes based on whether the move uses IEEE 128-bit floating e
	point or IBM 128-bit floating point type.
	(extendtfif2_internal): Likewise.
	(extendtfkf2_internal): Likewise.
---
 gcc/config/rs6000/rs6000.md | 94 +++++++++++++++++++++++++++++--------
 1 file changed, 74 insertions(+), 20 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f942597c3b4..e17252bb8de 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -543,12 +543,6 @@ (define_mode_iterator FMOVE128_GPR [TI
 ; Iterator for 128-bit VSX types for pack/unpack
 (define_mode_iterator FMOVE128_VSX [V1TI KF])
 
-; Iterators for converting to/from TFmode
-(define_mode_iterator IFKF [IF KF])
-
-; Constraints for moving IF/KFmode.
-(define_mode_attr IFKF_reg [(IF "d") (KF "wa")])
-
 ; Whether a floating point move is ok, don't allow SD without hardware FP
 (define_mode_attr fmove_ok [(SF "")
 			    (DF "")
@@ -9075,6 +9069,15 @@ (define_expand "extendifkf2"
   DONE;
 })
 
+(define_expand "extendkfif2"
+  [(set (match_operand:IF 0 "gpc_reg_operand")
+	(float_extend:IF (match_operand:KF 1 "gpc_reg_operand")))]
+  "TARGET_FLOAT128_TYPE"
+{
+  rs6000_expand_float128_convert (operands[0], operands[1], false);
+  DONE;
+})
+
 (define_expand "extendtfkf2"
   [(set (match_operand:KF 0 "gpc_reg_operand")
 	(float_extend:KF (match_operand:TF 1 "gpc_reg_operand")))]
@@ -9111,6 +9114,15 @@ (define_expand "truncifkf2"
   DONE;
 })
 
+(define_expand "trunckfif2"
+  [(set (match_operand:IF 0 "gpc_reg_operand")
+	(float_truncate:IF (match_operand:KF 1 "gpc_reg_operand")))]
+  "TARGET_FLOAT128_TYPE"
+{
+  rs6000_expand_float128_convert (operands[0], operands[1], false);
+  DONE;
+})
+
 (define_expand "trunckftf2"
   [(set (match_operand:TF 0 "gpc_reg_operand")
 	(float_truncate:TF (match_operand:KF 1 "gpc_reg_operand")))]
@@ -9129,31 +9141,73 @@ (define_expand "trunctfif2"
   DONE;
 })
 
-(define_insn_and_split "*extend<mode>tf2_internal"
-  [(set (match_operand:TF 0 "gpc_reg_operand" "=<IFKF_reg>")
+;; Convert between KFmode and TFmode when -mabi=ieeelongdouble
+(define_insn_and_split "*extendkftf2_internal"
+  [(set (match_operand:TF 0 "gpc_reg_operand" "=wa,wa")
 	(float_extend:TF
-	 (match_operand:IFKF 1 "gpc_reg_operand" "<IFKF_reg>")))]
-   "TARGET_FLOAT128_TYPE
-    && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (<MODE>mode)"
+	 (match_operand:KF 1 "gpc_reg_operand" "0,wa")))]
+   "FLOAT128_IEEE_P (TFmode)"
   "#"
   "&& reload_completed"
   [(set (match_dup 0) (match_dup 2))]
 {
   operands[2] = gen_rtx_REG (TFmode, REGNO (operands[1]));
-})
+}
+  [(set_attr "type" "vecsimple")])
 
-(define_insn_and_split "*extendtf<mode>2_internal"
-  [(set (match_operand:IFKF 0 "gpc_reg_operand" "=<IFKF_reg>")
-	(float_extend:IFKF
-	 (match_operand:TF 1 "gpc_reg_operand" "<IFKF_reg>")))]
-   "TARGET_FLOAT128_TYPE
-    && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (<MODE>mode)"
+(define_insn_and_split "*extendtfkf2_internal"
+  [(set (match_operand:KF 0 "gpc_reg_operand" "=wa,wa")
+	(float_extend:KF
+	 (match_operand:TF 1 "gpc_reg_operand" "0,wa")))]
+   "FLOAT128_IEEE_P (TFmode)"
   "#"
   "&& reload_completed"
   [(set (match_dup 0) (match_dup 2))]
 {
-  operands[2] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
-})
+  operands[2] = gen_rtx_REG (KFmode, REGNO (operands[1]));
+}
+  [(set_attr "type" "vecsimple")])
+
+;; Convert between IFmode and TFmode when -mabi=ibmlongdouble
+(define_insn_and_split "*extendiftf2_internal"
+  [(set (match_operand:TF 0 "gpc_reg_operand" "=d,&d")
+	(float_extend:TF
+	 (match_operand:IF 1 "input_operand" "0,d")))]
+   "FLOAT128_IBM_P (TFmode)"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 2) (match_dup 3))
+   (set (match_dup 4) (match_dup 5))]
+{
+  unsigned int op0_regno = reg_or_subregno (operands[0]);
+  unsigned int op1_regno = reg_or_subregno (operands[1]); 
+  operands[2] = gen_rtx_REG (DFmode, op0_regno);
+  operands[3] = gen_rtx_REG (DFmode, op1_regno);
+  operands[4] = gen_rtx_REG (DFmode, op0_regno + 1);
+  operands[5] = gen_rtx_REG (DFmode, op1_regno + 1);
+}
+  [(set_attr "type" "two")
+   (set_attr "num_insns" "2")])
+
+(define_insn_and_split "*extendtfif2_internal"
+  [(set (match_operand:IF 0 "gpc_reg_operand" "=d,&d")
+	(float_extend:IF
+	 (match_operand:TF 1 "input_operand" "0,d")))]
+   "FLOAT128_IBM_P (TFmode)"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 2) (match_dup 3))
+   (set (match_dup 4) (match_dup 5))]
+{
+  unsigned int op0_regno = reg_or_subregno (operands[0]);
+  unsigned int op1_regno = reg_or_subregno (operands[1]); 
+  operands[2] = gen_rtx_REG (DFmode, op0_regno);
+  operands[3] = gen_rtx_REG (DFmode, op1_regno);
+  operands[4] = gen_rtx_REG (DFmode, op0_regno + 1);
+  operands[5] = gen_rtx_REG (DFmode, op1_regno + 1);
+}
+  [(set_attr "type" "two")
+   (set_attr "num_insns" "2")])
 
 
 ;; Reload helper functions used by rs6000_secondary_reload.  The patterns all
-- 
2.37.2


-- 
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meissner@linux.ibm.com


More information about the Gcc-patches mailing list