[PATCH] RISC-V: Fix the sge<u> ..., x0, ... pattern

[Kito Cheng]

LGTM, that's apparently some kind of copy & paste error (from *slt<u>
pattern) when we add this pattern.

On Sun, Aug 7, 2022 at 3:42 AM Palmer Dabbelt <palmer@rivosinc.com> wrote:
>
> There's no operand 2 here, so referencing it doesn't make sense.  I
> couldn't find a way to trigger bad assembly output so I don't have a
> test.
>
> gcc/ChangeLog
>
>         PR target/106543
>         * config/riscv/riscv.md (sge<u>_<X:mode><GPR:mode>): Remove
>         reference to non-existent operand.
> ---
> No new failures on the Linux multilibs on trunk.
> ---
>  gcc/config/riscv/riscv.md | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 0796f91dd30..ed1c7f241e6 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -2386,7 +2386,7 @@
>         (any_ge:GPR (match_operand:X 1 "register_operand" " r")
>                     (const_int 1)))]
>    ""
> -  "slt%i2<u>\t%0,zero,%1"
> +  "slt<u>\t%0,zero,%1"
>    [(set_attr "type" "slt")
>     (set_attr "mode" "<X:MODE>")])
>
> --
> 2.34.1
>