[PATCH 03/21] [crypto]: add machine description for Zknd and Zkne
siyu@isrc.iscas.ac.cn
siyu@isrc.iscas.ac.cn
Sun Oct 31 09:34:27 GMT 2021
From: SiYu Wu <siyu@isrc.iscas.ac.cn>
---
gcc/common/config/riscv/riscv-common.c | 6 ++
gcc/config/riscv/crypto.md | 129 +++++++++++++++++++++++++
gcc/config/riscv/riscv-opts.h | 6 ++
gcc/config/riscv/riscv.md | 2 +
gcc/config/riscv/riscv.opt | 3 +
5 files changed, 146 insertions(+)
create mode 100644 gcc/config/riscv/crypto.md
diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
index 37b6ea80086..1e81847ee5c 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -106,6 +106,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zkne", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zknd", ISA_SPEC_CLASS_NONE, 1, 0},
+
/* Terminate the list. */
{NULL, ISA_SPEC_CLASS_NONE, 0, 0}
};
@@ -916,6 +919,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC},
{"zbs", &gcc_options::x_riscv_zb_subext, MASK_ZBS},
+ {"zknd", &gcc_options::x_riscv_zk_subext, MASK_ZKND},
+ {"zkne", &gcc_options::x_riscv_zk_subext, MASK_ZKNE},
+
{NULL, NULL, 0}
};
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
new file mode 100644
index 00000000000..170be7ff56c
--- /dev/null
+++ b/gcc/config/riscv/crypto.md
@@ -0,0 +1,129 @@
+;; Machine description for K extension.
+;; Copyright (C) 2021 Free Software Foundation, Inc.
+;; Contributed by SiYu Wu (siyu@isrc.iscas.ac.cn).
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+
+(define_c_enum "unspec" [
+ ;; Crypto extension unspecs.
+ UNSPEC_AES_DS
+ UNSPEC_AES_DSM
+ UNSPEC_AES_ES
+ UNSPEC_AES_ESM
+ UNSPEC_AES_IM
+ UNSPEC_AES_KS1
+ UNSPEC_AES_KS2
+])
+
+
+;; Zkne&Zknd - AES (RV32)
+
+(define_insn "riscv_aes32dsi"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "immediate_operand" "")]
+ UNSPEC_AES_DS))]
+ "TARGET_ZKND && !TARGET_64BIT"
+ "aes32dsi\t%0,%1,%2,%3")
+
+(define_insn "riscv_aes32dsmi"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "immediate_operand" "")]
+ UNSPEC_AES_DSM))]
+ "TARGET_ZKND && !TARGET_64BIT"
+ "aes32dsmi\t%0,%1,%2,%3")
+
+(define_insn "riscv_aes32esi"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "")
+ (match_operand:SI 3 "immediate_operand" "")]
+ UNSPEC_AES_ES))]
+ "TARGET_ZKNE && !TARGET_64BIT"
+ "aes32esi\t%0,%1,%2,%3")
+
+(define_insn "riscv_aes32esmi"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "immediate_operand" "")]
+ UNSPEC_AES_ESM))]
+ "TARGET_ZKNE && !TARGET_64BIT"
+ "aes32esmi\t%0,%1,%2,%3")
+
+
+;; Zkne&Zknd - AES (RV64)
+
+(define_insn "riscv_aes64ds"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "register_operand" "r")]
+ UNSPEC_AES_DS))]
+ "TARGET_ZKND && TARGET_64BIT"
+ "aes64ds\t%0,%1,%2")
+
+(define_insn "riscv_aes64dsm"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "register_operand" "r")]
+ UNSPEC_AES_DSM))]
+ "TARGET_ZKND && TARGET_64BIT"
+ "aes64dsm\t%0,%1,%2")
+
+(define_insn "riscv_aes64es"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "register_operand" "r")]
+ UNSPEC_AES_ES))]
+ "TARGET_ZKNE && TARGET_64BIT"
+ "aes64es\t%0,%1,%2")
+
+(define_insn "riscv_aes64esm"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "register_operand" "r")]
+ UNSPEC_AES_ESM))]
+ "TARGET_ZKNE && TARGET_64BIT"
+ "aes64esm\t%0,%1,%2")
+
+(define_insn "riscv_aes64im"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+ UNSPEC_AES_IM))]
+ "TARGET_ZKND && TARGET_64BIT"
+ "aes64im\t%0,%1")
+
+(define_insn "riscv_aes64ks1i"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "immediate_operand" "")]
+ UNSPEC_AES_KS1))]
+ "TARGET_ZKNE && TARGET_64BIT"
+ "aes64ks1i\t%0,%1,%2")
+
+(define_insn "riscv_aes64ks2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "register_operand" "r")]
+ UNSPEC_AES_KS2))]
+ "TARGET_ZKNE && TARGET_64BIT"
+ "aes64ks2\t%0,%1,%2")
+
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 2efc4b80f1f..b0226335c4f 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -83,4 +83,10 @@ enum stack_protector_guard {
#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
+#define MASK_ZKNE (1 << 5)
+#define MASK_ZKND (1 << 6)
+
+#define TARGET_ZKNE ((riscv_zk_subext & MASK_ZKNE) != 0)
+#define TARGET_ZKND ((riscv_zk_subext & MASK_ZKND) != 0)
+
#endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 1a786f31258..f95505d07da 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2765,6 +2765,8 @@ (define_insn "stack_tie<mode>"
[(set_attr "length" "0")]
)
+(include "crypto.md")
+
;; This fixes a failure with gcc.c-torture/execute/pr64242.c at -O2 for a
;; 32-bit target when using -mtune=sifive-7-series. The first sched pass
;; runs before register elimination, and we have a non-obvious dependency
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 15bf89e17c2..617000975bf 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -198,6 +198,9 @@ int riscv_zi_subext
TargetVariable
int riscv_zb_subext
+TargetVariable
+int riscv_zk_subext
+
Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):
--
2.25.1
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