[PATCH 13/13] arm: Convert more MVE/CDE builtins to predicate qualifiers
Richard Sandiford
richard.sandiford@arm.com
Mon Oct 11 14:21:56 GMT 2021
Christophe Lyon via Gcc-patches <gcc-patches@gcc.gnu.org> writes:
> This patch covers a few non-load/store builtins where we do not use
> the <mode> iterator and thus we cannot use <MVE_vpred>.
>
> We need to update the expected code in cde-mve-full-assembly.c because
> we now use mve_movv16qi instead of movhi to generate the vmsr
> instruction.
>
> 2021-09-02 Christophe Lyon <christophe.lyon@foss.st.com>
>
> gcc/
> PR target/100757
> PR target/101325
> * config/arm/arm-builtins.c (CX_UNARY_UNONE_QUALIFIERS): Use
> predicate.
> (CX_BINARY_UNONE_QUALIFIERS): Likewise.
> (CX_TERNARY_UNONE_QUALIFIERS): Likewise.
> (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Delete.
> (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Delete.
> (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Delete.
> * config/arm/arm_mve_builtins.def: Use predicated qualifiers.
> * config/arm/mve.md: Use VxBI instead of HI.
>
> gcc/testsuite/
> * gcc.target/arm/acle/cde-mve-full-assembly.c: Remove expected '@ movhi'.
OK, thanks.
Richard
> diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
> index e58580bb828..d725458f1ad 100644
> --- a/gcc/config/arm/arm-builtins.c
> +++ b/gcc/config/arm/arm-builtins.c
> @@ -344,7 +344,7 @@ static enum arm_type_qualifiers
> arm_cx_unary_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> = { qualifier_none, qualifier_immediate, qualifier_none,
> qualifier_unsigned_immediate,
> - qualifier_unsigned };
> + qualifier_predicate };
> #define CX_UNARY_UNONE_QUALIFIERS (arm_cx_unary_unone_qualifiers)
>
> /* T (immediate, T, T, unsigned immediate). */
> @@ -353,7 +353,7 @@ arm_cx_binary_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> = { qualifier_none, qualifier_immediate,
> qualifier_none, qualifier_none,
> qualifier_unsigned_immediate,
> - qualifier_unsigned };
> + qualifier_predicate };
> #define CX_BINARY_UNONE_QUALIFIERS (arm_cx_binary_unone_qualifiers)
>
> /* T (immediate, T, T, T, unsigned immediate). */
> @@ -362,7 +362,7 @@ arm_cx_ternary_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> = { qualifier_none, qualifier_immediate,
> qualifier_none, qualifier_none, qualifier_none,
> qualifier_unsigned_immediate,
> - qualifier_unsigned };
> + qualifier_predicate };
> #define CX_TERNARY_UNONE_QUALIFIERS (arm_cx_ternary_unone_qualifiers)
>
> /* The first argument (return type) of a store should be void type,
> @@ -558,12 +558,6 @@ arm_ternop_none_none_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> #define TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS \
> (arm_ternop_none_none_none_imm_qualifiers)
>
> -static enum arm_type_qualifiers
> -arm_ternop_none_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> - = { qualifier_none, qualifier_none, qualifier_none, qualifier_unsigned };
> -#define TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS \
> - (arm_ternop_none_none_none_unone_qualifiers)
> -
> static enum arm_type_qualifiers
> arm_ternop_none_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> = { qualifier_none, qualifier_none, qualifier_none, qualifier_predicate };
> @@ -616,13 +610,6 @@ arm_quadop_unone_unone_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> #define QUADOP_UNONE_UNONE_NONE_NONE_PRED_QUALIFIERS \
> (arm_quadop_unone_unone_none_none_pred_qualifiers)
>
> -static enum arm_type_qualifiers
> -arm_quadop_none_none_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> - = { qualifier_none, qualifier_none, qualifier_none, qualifier_none,
> - qualifier_unsigned };
> -#define QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS \
> - (arm_quadop_none_none_none_none_unone_qualifiers)
> -
> static enum arm_type_qualifiers
> arm_quadop_none_none_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> = { qualifier_none, qualifier_none, qualifier_none, qualifier_none,
> @@ -637,13 +624,6 @@ arm_quadop_none_none_none_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> #define QUADOP_NONE_NONE_NONE_IMM_PRED_QUALIFIERS \
> (arm_quadop_none_none_none_imm_pred_qualifiers)
>
> -static enum arm_type_qualifiers
> -arm_quadop_unone_unone_unone_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> - = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned,
> - qualifier_unsigned, qualifier_unsigned };
> -#define QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS \
> - (arm_quadop_unone_unone_unone_unone_unone_qualifiers)
> -
> static enum arm_type_qualifiers
> arm_quadop_unone_unone_unone_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS]
> = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned,
> diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def
> index bb79edf83ca..0fb53d866ec 100644
> --- a/gcc/config/arm/arm_mve_builtins.def
> +++ b/gcc/config/arm/arm_mve_builtins.def
> @@ -87,8 +87,8 @@ VAR4 (BINOP_UNONE_UNONE_UNONE, vcreateq_u, v16qi, v8hi, v4si, v2di)
> VAR4 (BINOP_NONE_UNONE_UNONE, vcreateq_s, v16qi, v8hi, v4si, v2di)
> VAR3 (BINOP_UNONE_UNONE_IMM, vshrq_n_u, v16qi, v8hi, v4si)
> VAR3 (BINOP_NONE_NONE_IMM, vshrq_n_s, v16qi, v8hi, v4si)
> -VAR1 (BINOP_NONE_NONE_UNONE, vaddlvq_p_s, v4si)
> -VAR1 (BINOP_UNONE_UNONE_UNONE, vaddlvq_p_u, v4si)
> +VAR1 (BINOP_NONE_NONE_PRED, vaddlvq_p_s, v4si)
> +VAR1 (BINOP_UNONE_UNONE_PRED, vaddlvq_p_u, v4si)
> VAR3 (BINOP_PRED_NONE_NONE, vcmpneq_, v16qi, v8hi, v4si)
> VAR3 (BINOP_NONE_NONE_NONE, vshlq_s, v16qi, v8hi, v4si)
> VAR3 (BINOP_UNONE_UNONE_NONE, vshlq_u, v16qi, v8hi, v4si)
> @@ -465,20 +465,20 @@ VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqshrnbq_n_s, v8hi, v4si)
> VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqrshrntq_n_s, v8hi, v4si)
> VAR2 (TERNOP_NONE_NONE_IMM_PRED, vorrq_m_n_s, v8hi, v4si)
> VAR2 (TERNOP_NONE_NONE_IMM_PRED, vmvnq_m_n_s, v8hi, v4si)
> -VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrmlaldavhq_p_u, v4si)
> -VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrev16q_m_u, v16qi)
> -VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vaddlvaq_p_u, v4si)
> -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlsldavhxq_p_s, v4si)
> -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlsldavhq_p_s, v4si)
> -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlaldavhxq_p_s, v4si)
> -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlaldavhq_p_s, v4si)
> -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrev32q_m_f, v8hf)
> -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrev16q_m_s, v16qi)
> -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvttq_m_f32_f16, v4sf)
> -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvttq_m_f16_f32, v8hf)
> -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvtbq_m_f32_f16, v4sf)
> -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvtbq_m_f16_f32, v8hf)
> -VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vaddlvaq_p_s, v4si)
> +VAR1 (TERNOP_UNONE_UNONE_UNONE_PRED, vrmlaldavhq_p_u, v4si)
> +VAR1 (TERNOP_UNONE_UNONE_UNONE_PRED, vrev16q_m_u, v16qi)
> +VAR1 (TERNOP_UNONE_UNONE_UNONE_PRED, vaddlvaq_p_u, v4si)
> +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrmlsldavhxq_p_s, v4si)
> +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrmlsldavhq_p_s, v4si)
> +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrmlaldavhxq_p_s, v4si)
> +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrmlaldavhq_p_s, v4si)
> +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrev32q_m_f, v8hf)
> +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrev16q_m_s, v16qi)
> +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vcvttq_m_f32_f16, v4sf)
> +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vcvttq_m_f16_f32, v8hf)
> +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vcvtbq_m_f32_f16, v4sf)
> +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vcvtbq_m_f16_f32, v8hf)
> +VAR1 (TERNOP_NONE_NONE_NONE_PRED, vaddlvaq_p_s, v4si)
> VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaxq_s, v4si)
> VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaq_s, v4si)
> VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlaldavhaxq_s, v4si)
> @@ -629,11 +629,11 @@ VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqshrntq_m_n_s, v8hi, v4si)
> VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqshrnbq_m_n_s, v8hi, v4si)
> VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqrshrntq_m_n_s, v8hi, v4si)
> VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqrshrnbq_m_n_s, v8hi, v4si)
> -VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vrmlaldavhaq_p_u, v4si)
> -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlsldavhaxq_p_s, v4si)
> -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlsldavhaq_p_s, v4si)
> -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlaldavhaxq_p_s, v4si)
> -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlaldavhaq_p_s, v4si)
> +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vrmlaldavhaq_p_u, v4si)
> +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrmlsldavhaxq_p_s, v4si)
> +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrmlsldavhaq_p_s, v4si)
> +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrmlaldavhaxq_p_s, v4si)
> +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrmlaldavhaq_p_s, v4si)
> VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_PRED, vcvtq_m_n_from_f_u, v8hi, v4si)
> VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vcvtq_m_n_from_f_s, v8hi, v4si)
> VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vbrsrq_m_n_f, v8hf, v4sf)
> @@ -845,14 +845,14 @@ VAR1 (BINOP_NONE_NONE_NONE, vsbciq_s, v4si)
> VAR1 (BINOP_UNONE_UNONE_UNONE, vsbciq_u, v4si)
> VAR1 (BINOP_NONE_NONE_NONE, vsbcq_s, v4si)
> VAR1 (BINOP_UNONE_UNONE_UNONE, vsbcq_u, v4si)
> -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vadciq_m_s, v4si)
> -VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vadciq_m_u, v4si)
> -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vadcq_m_s, v4si)
> -VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vadcq_m_u, v4si)
> -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsbciq_m_s, v4si)
> -VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsbciq_m_u, v4si)
> -VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsbcq_m_s, v4si)
> -VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsbcq_m_u, v4si)
> +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vadciq_m_s, v4si)
> +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vadciq_m_u, v4si)
> +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vadcq_m_s, v4si)
> +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vadcq_m_u, v4si)
> +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vsbciq_m_s, v4si)
> +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vsbciq_m_u, v4si)
> +VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vsbcq_m_s, v4si)
> +VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vsbcq_m_u, v4si)
> VAR5 (STORE1, vst2q, v16qi, v8hi, v4si, v8hf, v4sf)
> VAR5 (LOAD1, vld4q, v16qi, v8hi, v4si, v8hf, v4sf)
> VAR5 (LOAD1, vld2q, v16qi, v8hi, v4si, v8hf, v4sf)
> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
> index 241195909da..f73b5f6f1f1 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -826,7 +826,7 @@ (define_insn "mve_vaddlvq_p_<supf>v4si"
> [
> (set (match_operand:DI 0 "s_register_operand" "=r")
> (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
> - (match_operand:HI 2 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 2 "vpr_register_operand" "Up")]
> VADDLVQ_P))
> ]
> "TARGET_HAVE_MVE"
> @@ -3751,7 +3751,7 @@ (define_insn "mve_vaddlvaq_p_<supf>v4si"
> (set (match_operand:DI 0 "s_register_operand" "=r")
> (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
> (match_operand:V4SI 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
> VADDLVAQ_P))
> ]
> "TARGET_HAVE_MVE"
> @@ -3961,7 +3961,7 @@ (define_insn "mve_vcvtbq_m_f16_f32v8hf"
> (set (match_operand:V8HF 0 "s_register_operand" "=w")
> (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
> (match_operand:V4SF 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
> VCVTBQ_M_F16_F32))
> ]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> @@ -3977,7 +3977,7 @@ (define_insn "mve_vcvtbq_m_f32_f16v4sf"
> (set (match_operand:V4SF 0 "s_register_operand" "=w")
> (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0")
> (match_operand:V8HF 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
> VCVTBQ_M_F32_F16))
> ]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> @@ -3993,7 +3993,7 @@ (define_insn "mve_vcvttq_m_f16_f32v8hf"
> (set (match_operand:V8HF 0 "s_register_operand" "=w")
> (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
> (match_operand:V4SF 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
> VCVTTQ_M_F16_F32))
> ]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> @@ -4009,7 +4009,7 @@ (define_insn "mve_vcvttq_m_f32_f16v4sf"
> (set (match_operand:V4SF 0 "s_register_operand" "=w")
> (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0")
> (match_operand:V8HF 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
> VCVTTQ_M_F32_F16))
> ]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> @@ -4607,7 +4607,7 @@ (define_insn "mve_vrev32q_m_fv8hf"
> (set (match_operand:V8HF 0 "s_register_operand" "=w")
> (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
> (match_operand:V8HF 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
> VREV32Q_M_F))
> ]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> @@ -4671,7 +4671,7 @@ (define_insn "mve_vrmlaldavhxq_p_sv4si"
> (set (match_operand:DI 0 "s_register_operand" "=r")
> (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
> (match_operand:V4SI 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
> VRMLALDAVHXQ_P_S))
> ]
> "TARGET_HAVE_MVE"
> @@ -4703,7 +4703,7 @@ (define_insn "mve_vrmlsldavhq_p_sv4si"
> (set (match_operand:DI 0 "s_register_operand" "=r")
> (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
> (match_operand:V4SI 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
> VRMLSLDAVHQ_P_S))
> ]
> "TARGET_HAVE_MVE"
> @@ -4719,7 +4719,7 @@ (define_insn "mve_vrmlsldavhxq_p_sv4si"
> (set (match_operand:DI 0 "s_register_operand" "=r")
> (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
> (match_operand:V4SI 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
> VRMLSLDAVHXQ_P_S))
> ]
> "TARGET_HAVE_MVE"
> @@ -4944,7 +4944,7 @@ (define_insn "mve_vrev16q_m_<supf>v16qi"
> (set (match_operand:V16QI 0 "s_register_operand" "=w")
> (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "0")
> (match_operand:V16QI 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:V16BI 3 "vpr_register_operand" "Up")]
> VREV16Q_M))
> ]
> "TARGET_HAVE_MVE"
> @@ -4976,7 +4976,7 @@ (define_insn "mve_vrmlaldavhq_p_<supf>v4si"
> (set (match_operand:DI 0 "s_register_operand" "=r")
> (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
> (match_operand:V4SI 2 "s_register_operand" "w")
> - (match_operand:HI 3 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
> VRMLALDAVHQ_P))
> ]
> "TARGET_HAVE_MVE"
> @@ -6245,7 +6245,7 @@ (define_insn "mve_vrmlaldavhaq_p_sv4si"
> (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
> (match_operand:V4SI 2 "s_register_operand" "w")
> (match_operand:V4SI 3 "s_register_operand" "w")
> - (match_operand:HI 4 "vpr_register_operand" "Up")]
> + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
> VRMLALDAVHAQ_P_S))
> ]
> "TARGET_HAVE_MVE"
> @@ -6568,7 +6568,7 @@ (define_insn "mve_vrmlaldavhaq_p_uv4si"
> (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
> (match_operand:V4SI 2 "s_register_operand" "w")
> (match_operand:V4SI 3 "s_register_operand" "w")
> - (match_operand:HI 4 "vpr_register_operand" "Up")]
> + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
> VRMLALDAVHAQ_P_U))
> ]
> "TARGET_HAVE_MVE"
> @@ -6585,7 +6585,7 @@ (define_insn "mve_vrmlaldavhaxq_p_sv4si"
> (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
> (match_operand:V4SI 2 "s_register_operand" "w")
> (match_operand:V4SI 3 "s_register_operand" "w")
> - (match_operand:HI 4 "vpr_register_operand" "Up")]
> + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
> VRMLALDAVHAXQ_P_S))
> ]
> "TARGET_HAVE_MVE"
> @@ -6602,7 +6602,7 @@ (define_insn "mve_vrmlsldavhaq_p_sv4si"
> (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
> (match_operand:V4SI 2 "s_register_operand" "w")
> (match_operand:V4SI 3 "s_register_operand" "w")
> - (match_operand:HI 4 "vpr_register_operand" "Up")]
> + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
> VRMLSLDAVHAQ_P_S))
> ]
> "TARGET_HAVE_MVE"
> @@ -6619,7 +6619,7 @@ (define_insn "mve_vrmlsldavhaxq_p_sv4si"
> (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
> (match_operand:V4SI 2 "s_register_operand" "w")
> (match_operand:V4SI 3 "s_register_operand" "w")
> - (match_operand:HI 4 "vpr_register_operand" "Up")]
> + (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
> VRMLSLDAVHAXQ_P_S))
> ]
> "TARGET_HAVE_MVE"
> @@ -7540,7 +7540,7 @@ (define_insn "mve_vldrhq_<supf><mode>"
> (define_insn "mve_vldrhq_z_fv8hf"
> [(set (match_operand:V8HF 0 "s_register_operand" "=w")
> (unspec:V8HF [(match_operand:V8HI 1 "mve_memory_operand" "Ux")
> - (match_operand:HI 2 "vpr_register_operand" "Up")]
> + (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
> VLDRHQ_F))
> ]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> @@ -8315,7 +8315,7 @@ (define_insn "mve_vstrwq_fv4sf"
> (define_insn "mve_vstrwq_p_fv4sf"
> [(set (match_operand:V4SI 0 "memory_operand" "=Ux")
> (unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")
> - (match_operand:HI 2 "vpr_register_operand" "Up")]
> + (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
> VSTRWQ_F))
> ]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> @@ -9856,7 +9856,7 @@ (define_insn "mve_vadciq_m_<supf>v4si"
> (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0")
> (match_operand:V4SI 2 "s_register_operand" "w")
> (match_operand:V4SI 3 "s_register_operand" "w")
> - (match_operand:HI 4 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 4 "vpr_register_operand" "Up")]
> VADCIQ_M))
> (set (reg:SI VFPCC_REGNUM)
> (unspec:SI [(const_int 0)]
> @@ -9892,7 +9892,7 @@ (define_insn "mve_vadcq_m_<supf>v4si"
> (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0")
> (match_operand:V4SI 2 "s_register_operand" "w")
> (match_operand:V4SI 3 "s_register_operand" "w")
> - (match_operand:HI 4 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 4 "vpr_register_operand" "Up")]
> VADCQ_M))
> (set (reg:SI VFPCC_REGNUM)
> (unspec:SI [(reg:SI VFPCC_REGNUM)]
> @@ -9929,7 +9929,7 @@ (define_insn "mve_vsbciq_m_<supf>v4si"
> (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
> (match_operand:V4SI 2 "s_register_operand" "w")
> (match_operand:V4SI 3 "s_register_operand" "w")
> - (match_operand:HI 4 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 4 "vpr_register_operand" "Up")]
> VSBCIQ_M))
> (set (reg:SI VFPCC_REGNUM)
> (unspec:SI [(const_int 0)]
> @@ -9965,7 +9965,7 @@ (define_insn "mve_vsbcq_m_<supf>v4si"
> (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
> (match_operand:V4SI 2 "s_register_operand" "w")
> (match_operand:V4SI 3 "s_register_operand" "w")
> - (match_operand:HI 4 "vpr_register_operand" "Up")]
> + (match_operand:V4BI 4 "vpr_register_operand" "Up")]
> VSBCQ_M))
> (set (reg:SI VFPCC_REGNUM)
> (unspec:SI [(reg:SI VFPCC_REGNUM)]
> @@ -10469,7 +10469,7 @@ (define_insn "arm_vcx1q<a>_p_v16qi"
> (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
> (match_operand:V16QI 2 "register_operand" "0")
> (match_operand:SI 3 "const_int_mve_cde1_operand" "i")
> - (match_operand:HI 4 "vpr_register_operand" "Up")]
> + (match_operand:V16BI 4 "vpr_register_operand" "Up")]
> CDE_VCX))]
> "TARGET_CDE && TARGET_HAVE_MVE"
> "vpst\;vcx1<a>t\\tp%c1, %q0, #%c3"
> @@ -10483,7 +10483,7 @@ (define_insn "arm_vcx2q<a>_p_v16qi"
> (match_operand:V16QI 2 "register_operand" "0")
> (match_operand:V16QI 3 "register_operand" "t")
> (match_operand:SI 4 "const_int_mve_cde2_operand" "i")
> - (match_operand:HI 5 "vpr_register_operand" "Up")]
> + (match_operand:V16BI 5 "vpr_register_operand" "Up")]
> CDE_VCX))]
> "TARGET_CDE && TARGET_HAVE_MVE"
> "vpst\;vcx2<a>t\\tp%c1, %q0, %q3, #%c4"
> @@ -10498,7 +10498,7 @@ (define_insn "arm_vcx3q<a>_p_v16qi"
> (match_operand:V16QI 3 "register_operand" "t")
> (match_operand:V16QI 4 "register_operand" "t")
> (match_operand:SI 5 "const_int_mve_cde3_operand" "i")
> - (match_operand:HI 6 "vpr_register_operand" "Up")]
> + (match_operand:V16BI 6 "vpr_register_operand" "Up")]
> CDE_VCX))]
> "TARGET_CDE && TARGET_HAVE_MVE"
> "vpst\;vcx3<a>t\\tp%c1, %q0, %q3, %q4, #%c5"
> diff --git a/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c b/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c
> index 501cc84da10..77ea2866ad2 100644
> --- a/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c
> +++ b/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c
> @@ -567,80 +567,80 @@
> contain back references). */
> /*
> ** test_cde_vcx1q_mfloat16x8_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1t p0, q0, #32
> ** bx lr
> */
> /*
> ** test_cde_vcx1q_mfloat32x4_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1t p0, q0, #32
> ** bx lr
> */
> /*
> ** test_cde_vcx1q_muint8x16_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1t p0, q0, #32
> ** bx lr
> */
> /*
> ** test_cde_vcx1q_muint16x8_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1t p0, q0, #32
> ** bx lr
> */
> /*
> ** test_cde_vcx1q_muint32x4_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1t p0, q0, #32
> ** bx lr
> */
> /*
> ** test_cde_vcx1q_muint64x2_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1t p0, q0, #32
> ** bx lr
> */
> /*
> ** test_cde_vcx1q_mint8x16_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1t p0, q0, #32
> ** bx lr
> */
> /*
> ** test_cde_vcx1q_mint16x8_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1t p0, q0, #32
> ** bx lr
> */
> /*
> ** test_cde_vcx1q_mint32x4_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1t p0, q0, #32
> ** bx lr
> */
> /*
> ** test_cde_vcx1q_mint64x2_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1t p0, q0, #32
> ** bx lr
> @@ -649,80 +649,80 @@
>
> /*
> ** test_cde_vcx1qa_mfloat16x8_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1at p0, q0, #32
> ** bx lr
> */
> /*
> ** test_cde_vcx1qa_mfloat32x4_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1at p0, q0, #32
> ** bx lr
> */
> /*
> ** test_cde_vcx1qa_muint8x16_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1at p0, q0, #32
> ** bx lr
> */
> /*
> ** test_cde_vcx1qa_muint16x8_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1at p0, q0, #32
> ** bx lr
> */
> /*
> ** test_cde_vcx1qa_muint32x4_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1at p0, q0, #32
> ** bx lr
> */
> /*
> ** test_cde_vcx1qa_muint64x2_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1at p0, q0, #32
> ** bx lr
> */
> /*
> ** test_cde_vcx1qa_mint8x16_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1at p0, q0, #32
> ** bx lr
> */
> /*
> ** test_cde_vcx1qa_mint16x8_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1at p0, q0, #32
> ** bx lr
> */
> /*
> ** test_cde_vcx1qa_mint32x4_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1at p0, q0, #32
> ** bx lr
> */
> /*
> ** test_cde_vcx1qa_mint64x2_tintint:
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> -** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2 @ movhi)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> +** (?:vldr\.64 d0, \.L[0-9]*\n\tvldr\.64 d1, \.L[0-9]*\+8|vmsr P0, r2)
> ** vpst
> ** vcx1at p0, q0, #32
> ** bx lr
> @@ -731,8 +731,8 @@
>
> /*
> ** test_cde_vcx2q_mfloat16x8_tuint16x8_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2t p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -740,8 +740,8 @@
> */
> /*
> ** test_cde_vcx2q_mfloat16x8_tfloat32x4_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2t p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -749,8 +749,8 @@
> */
> /*
> ** test_cde_vcx2q_mfloat32x4_tuint8x16_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2t p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -758,8 +758,8 @@
> */
> /*
> ** test_cde_vcx2q_mint64x2_tuint8x16_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2t p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -767,8 +767,8 @@
> */
> /*
> ** test_cde_vcx2q_mint8x16_tuint8x16_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2t p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -776,8 +776,8 @@
> */
> /*
> ** test_cde_vcx2q_muint16x8_tuint8x16_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2t p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -785,8 +785,8 @@
> */
> /*
> ** test_cde_vcx2q_muint8x16_tint64x2_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2t p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -794,8 +794,8 @@
> */
> /*
> ** test_cde_vcx2q_muint8x16_tint8x16_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2t p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -803,8 +803,8 @@
> */
> /*
> ** test_cde_vcx2q_muint8x16_tuint16x8_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2t p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -812,8 +812,8 @@
> */
> /*
> ** test_cde_vcx2q_muint8x16_tuint8x16_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2t p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -823,8 +823,8 @@
>
> /*
> ** test_cde_vcx2qa_mfloat16x8_tuint16x8_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2at p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -832,8 +832,8 @@
> */
> /*
> ** test_cde_vcx2qa_mfloat16x8_tfloat32x4_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2at p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -841,8 +841,8 @@
> */
> /*
> ** test_cde_vcx2qa_mfloat32x4_tuint8x16_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2at p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -850,8 +850,8 @@
> */
> /*
> ** test_cde_vcx2qa_mint64x2_tuint8x16_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2at p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -859,8 +859,8 @@
> */
> /*
> ** test_cde_vcx2qa_mint8x16_tuint8x16_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2at p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -868,8 +868,8 @@
> */
> /*
> ** test_cde_vcx2qa_muint16x8_tuint8x16_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2at p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -877,8 +877,8 @@
> */
> /*
> ** test_cde_vcx2qa_muint8x16_tint64x2_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2at p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -886,8 +886,8 @@
> */
> /*
> ** test_cde_vcx2qa_muint8x16_tint8x16_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2at p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -895,8 +895,8 @@
> */
> /*
> ** test_cde_vcx2qa_muint8x16_tuint16x8_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2at p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -904,8 +904,8 @@
> */
> /*
> ** test_cde_vcx2qa_muint8x16_tuint8x16_tint:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r1)
> ** vpst
> ** vcx2at p0, (q[0-7]), q0, #32
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -915,8 +915,8 @@
>
> /*
> ** test_cde_vcx3q_muint8x16_tuint8x16_tuint8x16_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3t p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -924,8 +924,8 @@
> */
> /*
> ** test_cde_vcx3q_mfloat16x8_tfloat16x8_tfloat16x8_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3t p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -933,8 +933,8 @@
> */
> /*
> ** test_cde_vcx3q_mfloat32x4_tuint64x2_tfloat16x8_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3t p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -942,8 +942,8 @@
> */
> /*
> ** test_cde_vcx3q_muint16x8_tuint8x16_tuint8x16_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3t p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -951,8 +951,8 @@
> */
> /*
> ** test_cde_vcx3q_muint8x16_tuint16x8_tuint8x16_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3t p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -960,8 +960,8 @@
> */
> /*
> ** test_cde_vcx3q_muint8x16_tuint8x16_tuint16x8_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3t p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -969,8 +969,8 @@
> */
> /*
> ** test_cde_vcx3q_mint8x16_tuint8x16_tuint8x16_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3t p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -978,8 +978,8 @@
> */
> /*
> ** test_cde_vcx3q_muint8x16_tint8x16_tuint8x16_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3t p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -987,8 +987,8 @@
> */
> /*
> ** test_cde_vcx3q_muint8x16_tuint8x16_tint8x16_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3t p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -996,8 +996,8 @@
> */
> /*
> ** test_cde_vcx3q_mint64x2_tuint8x16_tuint8x16_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3t p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -1005,8 +1005,8 @@
> */
> /*
> ** test_cde_vcx3q_muint8x16_tint64x2_tuint8x16_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3t p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -1014,8 +1014,8 @@
> */
> /*
> ** test_cde_vcx3q_muint8x16_tuint8x16_tint64x2_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3t p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -1023,8 +1023,8 @@
> */
> /*
> ** test_cde_vcx3q_muint8x16_tint64x2_tint64x2_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3t p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -1034,8 +1034,8 @@
>
> /*
> ** test_cde_vcx3qa_muint8x16_tuint8x16_tuint8x16_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3at p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -1043,8 +1043,8 @@
> */
> /*
> ** test_cde_vcx3qa_mfloat16x8_tfloat16x8_tfloat16x8_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3at p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -1052,8 +1052,8 @@
> */
> /*
> ** test_cde_vcx3qa_mfloat32x4_tuint64x2_tfloat16x8_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3at p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -1061,8 +1061,8 @@
> */
> /*
> ** test_cde_vcx3qa_muint16x8_tuint8x16_tuint8x16_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3at p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -1070,8 +1070,8 @@
> */
> /*
> ** test_cde_vcx3qa_muint8x16_tuint16x8_tuint8x16_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3at p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -1079,8 +1079,8 @@
> */
> /*
> ** test_cde_vcx3qa_muint8x16_tuint8x16_tuint16x8_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3at p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -1088,8 +1088,8 @@
> */
> /*
> ** test_cde_vcx3qa_mint8x16_tuint8x16_tuint8x16_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3at p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -1097,8 +1097,8 @@
> */
> /*
> ** test_cde_vcx3qa_muint8x16_tint8x16_tuint8x16_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3at p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -1106,8 +1106,8 @@
> */
> /*
> ** test_cde_vcx3qa_muint8x16_tuint8x16_tint8x16_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3at p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -1115,8 +1115,8 @@
> */
> /*
> ** test_cde_vcx3qa_mint64x2_tuint8x16_tuint8x16_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3at p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -1124,8 +1124,8 @@
> */
> /*
> ** test_cde_vcx3qa_muint8x16_tint64x2_tuint8x16_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3at p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -1133,8 +1133,8 @@
> */
> /*
> ** test_cde_vcx3qa_muint8x16_tuint8x16_tint64x2_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3at p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
> @@ -1142,8 +1142,8 @@
> */
> /*
> ** test_cde_vcx3qa_muint8x16_tint64x2_tint64x2_t:
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> -** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0 @ movhi)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> +** (?:vldr\.64 d(?:[02468]|1[024]), \.L[0-9]*\n\tvldr\.64 d(?:[13579]|1[135]), \.L[0-9]*\+8|vmsr P0, r0)
> ** vpst
> ** vcx3at p0, (q[0-7]), q0, q1, #15
> ** vmov q0, \1([[:space:]]+@ [^\n]*)?
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