[PATCH] [i386] Fix ICE in ix86_attr_length_immediate_default.

liuhongt hongtao.liu@intel.com
Tue Nov 30 09:43:29 GMT 2021


ix86_attr_length_immediate_default assume TYPE ishift only have 1
constant operand,
but *x86_64_shld_1/*x86_shld_1/*x86_64_shrd_1/*x86_shrd_1 has 2, with
condition: INTVAL (operands[3]) == 32 - INTVAL (operands[2]) or
INTVAL (operands[3]) == 64 - INTVAL (operands[2]), and hit
gcc_assert.
Explicitly set_attr length_immediate for these patterns.

Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ok for trunk?


gcc/ChangeLog:

	PR target/103463
	PR target/103484
	* config/i386/i386.md (*x86_64_shld_1): Set_attr
	length_immediate to 1.
	(*x86_shld_1): Ditto.
	(*x86_64_shrd_1): Ditto.
	(*x86_shrd_1): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr103463.c: New test.
	* gcc.target/i386/pr103463-2.c: New test.
---
 gcc/config/i386/i386.md                    |  4 ++++
 gcc/testsuite/gcc.target/i386/pr103463-2.c | 14 ++++++++++++++
 gcc/testsuite/gcc.target/i386/pr103463.c   | 13 +++++++++++++
 3 files changed, 31 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr103463-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr103463.c

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index c88374c9d2b..4e9fae80479 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -11512,6 +11512,7 @@ (define_insn "*x86_64_shld_1"
   [(set_attr "type" "ishift")
    (set_attr "prefix_0f" "1")
    (set_attr "mode" "DI")
+   (set_attr "length_immediate" "1")
    (set_attr "athlon_decode" "vector")
    (set_attr "amdfam10_decode" "vector")
    (set_attr "bdver1_decode" "vector")])
@@ -11573,6 +11574,7 @@ (define_insn "*x86_shld_1"
   "shld{l}\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ishift")
    (set_attr "prefix_0f" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "SI")
    (set_attr "pent_pair" "np")
    (set_attr "athlon_decode" "vector")
@@ -12384,6 +12386,7 @@ (define_insn "*x86_64_shrd_1"
   "shrd{q}\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ishift")
    (set_attr "prefix_0f" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "DI")
    (set_attr "athlon_decode" "vector")
    (set_attr "amdfam10_decode" "vector")
@@ -12446,6 +12449,7 @@ (define_insn "*x86_shrd_1"
   "shrd{l}\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ishift")
    (set_attr "prefix_0f" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "SI")
    (set_attr "pent_pair" "np")
    (set_attr "athlon_decode" "vector")
diff --git a/gcc/testsuite/gcc.target/i386/pr103463-2.c b/gcc/testsuite/gcc.target/i386/pr103463-2.c
new file mode 100644
index 00000000000..9c29b70bbd8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr103463-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -fno-tree-bit-ccp" } */
+
+int foo_u64_1;
+unsigned __int128 foo_u128_1;
+
+void
+foo (void)
+{
+  foo_u128_1 <<= 127;
+  foo_u64_1 += __builtin_sub_overflow_p (0, (long) foo_u128_1, 0);
+  foo_u128_1 =
+    foo_u128_1 >> (foo_u128_1 & 127) | foo_u128_1 << (-foo_u128_1 & 127);
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr103463.c b/gcc/testsuite/gcc.target/i386/pr103463.c
new file mode 100644
index 00000000000..faae9a858e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr103463.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-Os -fno-tree-dominator-opts -fno-tree-vrp" } */
+
+int bar0_u8_0, bar0_u16_0, bar0_u32_0, bar0_u16_1, bar0_u32_1;
+unsigned __int128 bar0_u128_0;
+
+int
+bar0() {
+  bar0_u16_1 *=
+      __builtin_add_overflow_p(bar0_u16_0, bar0_u32_1, (long)bar0_u8_0);
+  bar0_u128_0 = bar0_u128_0 >> bar0_u16_1 | bar0_u128_0 << (-bar0_u16_1 & 127);
+  bar0_u128_0 += __builtin_mul_overflow_p(bar0_u32_0, 20, 0);
+}
-- 
2.18.1



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