[PATCH v1 6/8] RISC-V: bitmanip: add splitter to use bexti for "(a & (1 << BIT_NO)) ? 0 : -1"

[Kito Cheng]

> --- a/gcc/config/riscv/bitmanip.md
> +++ b/gcc/config/riscv/bitmanip.md
> @@ -367,3 +367,16 @@ (define_insn "*bexti"
>    "TARGET_ZBS"
>    "bexti\t%0,%1,%2"
>    [(set_attr "type" "bitmanip")])
> +
> +;; We can create a polarity-reversed mask (i.e. bit N -> { set = 0, clear = -1 })
> +;; using a bext(i) followed by an addi instruction.
> +;; This splits the canonical representation of "(a & (1 << BIT_NO)) ? 0 : -1".
> +(define_split
> +  [(set (match_operand:GPR 0 "register_operand")
> +       (neg:GPR (eq:GPR (zero_extract:GPR (match_operand:GPR 1 "register_operand")
> +                                          (const_int 1)
> +                                          (match_operand 2))
> +                        (const_int 0))))]
> +  "TARGET_ZBB"

Should be TARGET_ZBS?

> +  [(set (match_dup 0) (zero_extract:GPR (match_dup 1) (const_int 1) (match_dup 2)))
> +   (set (match_dup 0) (plus:GPR (match_dup 0) (const_int -1)))])
> diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c
> new file mode 100644
> index 00000000000..d02c3f7a98d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */
> +
> +/* bexti */
> +#define BIT_NO  27
> +
> +long
> +foo0 (long a)
> +{
> +  return (a & (1 << BIT_NO)) ? 0 : -1;

I got the same code gen for rv64gc_zbs both w/ and w/o this patch,
but got better code gen when I changed BIT_NO to 4,
so I guess we should use 4 rather than 27 for demonstrating this patch?

long
foo2 (long a)
{
 return (a & (1 << 4)) ? 0 : -1;
}