[PATCH][GCC] aarch64: Add new vector mode V8DI

[Przemyslaw Wirkus]

Hi,
This patch is adding new V8DI mode which will be used with new Armv8.7-A
LS64 extension intrinsics.

Regtested on aarch64-elf and no issues.

OK for master?

gcc/ChangeLog:

2021-11-10  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* config/aarch64/aarch64-modes.def (VECTOR_MODE): New V8DI mode.
	* config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Handle
	V8DImode.
	* config/aarch64/iterators.md (define_mode_attr nunits): Add entry
	for V8DI.

Kind regards,
Przemyslaw Wirkus

--- 

diff --git a/gcc/config/aarch64/aarch64-modes.def b/gcc/config/aarch64/aarch64-modes.def
index ac97d222789c6701d858c014736f8c211512a4d9..62595b8af6e1eea8fc769885bba9fe54f0a9ec05 100644
--- a/gcc/config/aarch64/aarch64-modes.def
+++ b/gcc/config/aarch64/aarch64-modes.def
@@ -81,6 +81,11 @@ INT_MODE (OI, 32);
 INT_MODE (CI, 48);
 INT_MODE (XI, 64);
 
+/* V8DI mode.  */
+VECTOR_MODE_WITH_PREFIX (V, INT, DI, 8, 5); \
+  \
+  ADJUST_ALIGNMENT (V8DI, 8);
+
 /* Define Advanced SIMD modes for structures of 2, 3 and 4 d-registers.  */
 #define ADV_SIMD_D_REG_STRUCT_MODES(NVECS, VB, VH, VS, VD) \
   VECTOR_MODES_WITH_PREFIX (V##NVECS##x, INT, 8, 3); \
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 69f08052ce808c140ed2933ab6b2e2617ca6f669..0e102a83a8dc34e715fafb58169897b12c9b3a20 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -3376,6 +3376,9 @@ aarch64_hard_regno_nregs (unsigned regno, machine_mode mode)
 static bool
 aarch64_hard_regno_mode_ok (unsigned regno, machine_mode mode)
 {
+  if (mode == V8DImode)
+    return IN_RANGE (regno, R0_REGNUM, R23_REGNUM);
+
   if (GET_MODE_CLASS (mode) == MODE_CC)
     return regno == CC_REGNUM;
 
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index bdc8ba3576cf2c9b4ae96b45a382234e4e25b13f..cea277f3a03cfd20178e51e6abd7e256e206299f 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -1053,7 +1053,7 @@ (define_mode_attr vas [(DI "") (SI ".2s")])
 (define_mode_attr nunits [(V8QI "8") (V16QI "16")
 			  (V4HI "4") (V8HI "8")
 			  (V2SI "2") (V4SI "4")
-				     (V2DI "2")
+			  (V2DI "2") (V8DI "8")
 			  (V4HF "4") (V8HF "8")
 			  (V4BF "4") (V8BF "8")
 			  (V2SF "2") (V4SF "4")