[PATCH] Fix vsx_splat_v4si in 32 bit mode

David Edelsohn dje.gcc@gmail.com
Sat Nov 6 15:43:11 GMT 2021

    powerpc: Fix vsx_splat_v4si in 32 bit mode

    Tamar's recent patch to teach CSE to perform vector extract exercises
    VSX splat more frequently, which exposed a constraint error for the
    vsx_splat patterns.  The pattern could be created for Power9, but
    the "we constraint only provided alternatives in 64 bit mode. The
    instructions are valid in 32 bit mode and SImode is allowed in VSX
    registers.  This patch updates the constraints from "we" to "wa" to
    allow the pattern and fix the failing testcases.

Bootstrapped on powerpc-ibm-aix7.2.3.0.


            * config/rs6000/vsx.md (vsx_splat_v4si): Change constraints to "wa".
            (vsx_splat_v4si_di): Change constraint to "wa"

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 0bf04feb6c4..a97f7f2a680 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4565,7 +4565,7 @@ (define_insn "vsx_splat_<mode>_mem"

 ;; V4SI splat support
 (define_insn "vsx_splat_v4si"
-  [(set (match_operand:V4SI 0 "vsx_register_operand" "=we,we")
+  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa")
         (match_operand:SI 1 "splat_input_operand" "r,Z")))]
@@ -4578,7 +4578,7 @@ (define_insn "vsx_splat_v4si"
 ;; allows us to use direct move to get the value in a vector register
 ;; so that we can use XXSPLTW
 (define_insn "vsx_splat_v4si_di"
-  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,we")
+  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa")
          (match_operand:DI 1 "gpc_reg_operand" "wa,r"))))]

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