[PATCH 02/21] Fix attribute bugs due to zicsr/zifencei

Kito Cheng kito.cheng@sifive.com
Tue Nov 2 10:42:40 GMT 2021


> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 225e5b259c1..1a786f31258 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -1812,7 +1812,7 @@ (define_expand "clear_cache"
>
>  (define_insn "fence"
>    [(unspec_volatile [(const_int 0)] UNSPECV_FENCE)]
> -  ""
> +  "TARGET_ZIFENCEI"
   "%|fence%-")

fence instruction is included in baseline ISA.
https://github.com/riscv/riscv-isa-manual/blob/master/src/rv32.tex#L1206


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