[PATCH 0/2] Add power10 IEEE 128-bit min/max/conditional move support

[Michael Meissner]

The following two patches are new versions of the patches I've submitted in the
past to add support for the power10 IEEE 128-bit XSMAXCQP, XSMINCQP, XSCMPEQQ,
XSCMPGTQ, and XSCMPGEQ instructions.

This time I'm not trying to share code with the DFmode/SFmode min, max, or
conditional move support.  One reason is going between VSX registers (SF/DF)
and Altivec registers (KF/TF) adds to the complexity.

The first patch adds support for the XSMINCQP and XSMAXCQP instructions.  GCC
will generate these instructions if a built-in function is used or if the use
has turned on fast math.

The second patch adds support for the XSCMPEQ, XSCMPGEQ, and XSCMPGTQ
instructions and conditional moves.  With conditional move support, the
compiler will generate XSMINCQP and XSMAXCQP more often without fast math.

Too keep the complexity down, the conditional move support only supports both
the type for the items being compare and the items being move being the same.
Note, there is code to allow SF/DF inter-mixing for contiional move, and that
is not changed with this patch.

I.e. for conditional move, this will use the XSCMPEQP and XXSEL instructions:

	__float128 cmp1, cmp2;
	__float128 result, move1, move2;
		/* ... */
	result = (cmp1 == cmp2) ? move1 : move2;

I have done bootstrap builds with this patch on the following 3 systems:
    1)	power9 running LE Linux using --with-cpu=power9
    2)	power8 running BE Linux using --with-cpu=power8, testing both
	32/64-bit.
    3)	power10 prototype running LE Linux using --with-cpu=power10.

There were no regressions to the tests, and the new test added passed.  Can I
check these patches into trunk branch for GCC 12?

I would like to check these patches into GCC 11 after a cooling off period, but
I can also not do the backport if desired.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797