[PATCH] rs6000: Enable 32bit variable vec_insert [PR99718]
Xionghu Luo
luoxhu@linux.ibm.com
Sat Mar 27 03:26:57 GMT 2021
From: "luoxhu@cn.ibm.com" <luoxhu@cn.ibm.com>
32bit and P7 VSX could also benefit a lot from the variable vec_insert
implementation with shift/insert/shift back method.
Tested pass on P7BE/P8BE/P8LE{-m32,m64} and P9LE{m64}.
gcc/ChangeLog:
PR target/99718
* config/rs6000/altivec.md (altivec_lvsl_reg): Change to ...
(altivec_lvsl_reg_<mode>): ... this.
(altivec_lvsr_reg): Change to ...
(altivec_lvsr_reg_<mode>): ... this.
* config/rs6000/predicates.md (vec_set_index_operand): New.
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
Enable 32bit variable vec_insert for all TARGET_VSX.
* config/rs6000/rs6000.c (rs6000_expand_vector_set_var_p9):
Enable 32bit variable vec_insert for p9 and above.
(rs6000_expand_vector_set_var_p8): Rename to ...
(rs6000_expand_vector_set_var_p7): ... this.
(rs6000_expand_vector_set): Use TARGET_VSX and adjust assert
position.
* config/rs6000/vector.md: Use vec_set_index_operand.
* config/rs6000/vsx.md: Use gen_altivec_lvsl_reg_di and
gen_altivec_lvsr_reg_di.
gcc/testsuite/ChangeLog:
PR target/99718
* gcc.target/powerpc/fold-vec-insert-char-p8.c: Update
instruction counts.
* gcc.target/powerpc/fold-vec-insert-char-p9.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-double.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-float-p8.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-float-p9.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-int-p8.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-int-p9.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-longlong.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-short-p8.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-short-p9.c: Likewise.
* gcc.target/powerpc/pr79251.p8.c: Likewise.
* gcc.target/powerpc/pr79251.p9.c: Likewise.
* gcc.target/powerpc/vsx-builtin-7.c: Likewise.
* gcc.target/powerpc/pr79251-run.p7.c: New test.
* gcc.target/powerpc/pr79251.p7.c: New test.
---
gcc/config/rs6000/altivec.md | 8 +-
gcc/config/rs6000/predicates.md | 6 ++
gcc/config/rs6000/rs6000-c.c | 2 +-
gcc/config/rs6000/rs6000.c | 89 +++++++++++++++----
gcc/config/rs6000/vector.md | 2 +-
gcc/config/rs6000/vsx.md | 4 +-
.../powerpc/fold-vec-insert-char-p8.c | 8 +-
.../powerpc/fold-vec-insert-char-p9.c | 4 +-
.../powerpc/fold-vec-insert-double.c | 18 ++--
.../powerpc/fold-vec-insert-float-p8.c | 4 +-
.../powerpc/fold-vec-insert-float-p9.c | 2 +-
.../powerpc/fold-vec-insert-int-p8.c | 6 +-
.../powerpc/fold-vec-insert-int-p9.c | 6 +-
.../powerpc/fold-vec-insert-longlong.c | 6 +-
.../powerpc/fold-vec-insert-short-p8.c | 6 +-
.../powerpc/fold-vec-insert-short-p9.c | 6 +-
.../gcc.target/powerpc/pr79251-run.p7.c | 15 ++++
gcc/testsuite/gcc.target/powerpc/pr79251.p7.c | 23 +++++
gcc/testsuite/gcc.target/powerpc/pr79251.p8.c | 10 +--
gcc/testsuite/gcc.target/powerpc/pr79251.p9.c | 6 +-
.../gcc.target/powerpc/vsx-builtin-7.c | 11 +--
21 files changed, 170 insertions(+), 72 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/powerpc/pr79251-run.p7.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/pr79251.p7.c
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 27a269b9e72..e9005d6e42e 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -2771,10 +2771,10 @@ (define_expand "altivec_lvsl"
DONE;
})
-(define_insn "altivec_lvsl_reg"
+(define_insn "altivec_lvsl_reg_<mode>"
[(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
(unspec:V16QI
- [(match_operand:DI 1 "gpc_reg_operand" "b")]
+ [(match_operand:SDI 1 "gpc_reg_operand" "b")]
UNSPEC_LVSL_REG))]
"TARGET_ALTIVEC"
"lvsl %0,0,%1"
@@ -2809,10 +2809,10 @@ (define_expand "altivec_lvsr"
DONE;
})
-(define_insn "altivec_lvsr_reg"
+(define_insn "altivec_lvsr_reg_<mode>"
[(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
(unspec:V16QI
- [(match_operand:DI 1 "gpc_reg_operand" "b")]
+ [(match_operand:SDI 1 "gpc_reg_operand" "b")]
UNSPEC_LVSR_REG))]
"TARGET_ALTIVEC"
"lvsr %0,0,%1"
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 859af75dfbd..4d8f660eea0 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -1940,3 +1940,9 @@ (define_predicate "d_form_memory"
return !indexed_address (addr, mode);
})
+
+;; Return true if TARGET_VSX for vec_set with variable index.
+(define_predicate "vec_set_index_operand"
+ (if_then_else (match_test "TARGET_VSX")
+ (match_operand 0 "reg_or_cint_operand")
+ (match_operand 0 "const_int_operand")))
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 06b3bc0df33..0f8a629ff5a 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -1602,7 +1602,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt);
}
- if (TARGET_P8_VECTOR && TARGET_DIRECT_MOVE_64BIT)
+ if (TARGET_VSX)
{
stmt = build_array_ref (loc, stmt, arg2);
stmt = fold_build2 (MODIFY_EXPR, TREE_TYPE (arg0), stmt,
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 34c4edae20e..dee37f37d99 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -7035,20 +7035,40 @@ rs6000_expand_vector_set_var_p9 (rtx target, rtx val, rtx idx)
int shift = exact_log2 (width);
machine_mode idx_mode = GET_MODE (idx);
- idx = convert_modes (DImode, idx_mode, idx, 1);
+ machine_mode shift_mode;
+ rtx (*gen_ashl)(rtx, rtx, rtx);
+ rtx (*gen_lvsl)(rtx, rtx);
+ rtx (*gen_lvsr)(rtx, rtx);
+
+ if (TARGET_POWERPC64)
+ {
+ shift_mode = DImode;
+ gen_ashl = gen_ashldi3;
+ gen_lvsl = gen_altivec_lvsl_reg_di;
+ gen_lvsr = gen_altivec_lvsr_reg_di;
+ }
+ else
+ {
+ shift_mode = SImode;
+ gen_ashl = gen_ashlsi3;
+ gen_lvsl = gen_altivec_lvsl_reg_si;
+ gen_lvsr = gen_altivec_lvsr_reg_si;
+ }
/* Generate the IDX for permute shift, width is the vector element size.
idx = idx * width. */
- rtx tmp = gen_reg_rtx (DImode);
- emit_insn (gen_ashldi3 (tmp, idx, GEN_INT (shift)));
+ rtx tmp = gen_reg_rtx (shift_mode);
+ idx = convert_modes (shift_mode, idx_mode, idx, 1);
+
+ emit_insn (gen_ashl (tmp, idx, GEN_INT (shift)));
/* lvsr v1,0,idx. */
rtx pcvr = gen_reg_rtx (V16QImode);
- emit_insn (gen_altivec_lvsr_reg (pcvr, tmp));
+ emit_insn (gen_lvsr (pcvr, tmp));
/* lvsl v2,0,idx. */
rtx pcvl = gen_reg_rtx (V16QImode);
- emit_insn (gen_altivec_lvsl_reg (pcvl, tmp));
+ emit_insn (gen_lvsl (pcvl, tmp));
rtx sub_target = simplify_gen_subreg (V16QImode, target, mode, 0);
@@ -7064,10 +7084,10 @@ rs6000_expand_vector_set_var_p9 (rtx target, rtx val, rtx idx)
}
/* Insert VAL into IDX of TARGET, VAL size is same of the vector element, IDX
- is variable and also counts by vector element size for p8. */
+ is variable and also counts by vector element size for p7 & p8. */
static void
-rs6000_expand_vector_set_var_p8 (rtx target, rtx val, rtx idx)
+rs6000_expand_vector_set_var_p7 (rtx target, rtx val, rtx idx)
{
machine_mode mode = GET_MODE (target);
@@ -7082,17 +7102,41 @@ rs6000_expand_vector_set_var_p8 (rtx target, rtx val, rtx idx)
int shift = exact_log2 (width);
machine_mode idx_mode = GET_MODE (idx);
- idx = convert_modes (DImode, idx_mode, idx, 1);
+
+ machine_mode shift_mode;
+ rtx (*gen_ashl)(rtx, rtx, rtx);
+ rtx (*gen_add)(rtx, rtx, rtx);
+ rtx (*gen_sub)(rtx, rtx, rtx);
+ rtx (*gen_lvsl)(rtx, rtx);
+
+ if (TARGET_POWERPC64)
+ {
+ shift_mode = DImode;
+ gen_ashl = gen_ashldi3;
+ gen_add = gen_adddi3;
+ gen_sub = gen_subdi3;
+ gen_lvsl = gen_altivec_lvsl_reg_di;
+ }
+ else
+ {
+ shift_mode = SImode;
+ gen_ashl = gen_ashlsi3;
+ gen_add = gen_addsi3;
+ gen_sub = gen_subsi3;
+ gen_lvsl = gen_altivec_lvsl_reg_si;
+ }
/* idx = idx * width. */
- rtx tmp = gen_reg_rtx (DImode);
- emit_insn (gen_ashldi3 (tmp, idx, GEN_INT (shift)));
+ rtx tmp = gen_reg_rtx (shift_mode);
+ idx = convert_modes (shift_mode, idx_mode, idx, 1);
+
+ emit_insn (gen_ashl (tmp, idx, GEN_INT (shift)));
/* For LE: idx = idx + 8. */
if (!BYTES_BIG_ENDIAN)
- emit_insn (gen_adddi3 (tmp, tmp, GEN_INT (8)));
+ emit_insn (gen_add (tmp, tmp, GEN_INT (8)));
else
- emit_insn (gen_subdi3 (tmp, GEN_INT (24 - width), tmp));
+ emit_insn (gen_sub (tmp, GEN_INT (24 - width), tmp));
/* lxv vs33, mask.
DImode: 0xffffffffffffffff0000000000000000
@@ -7119,7 +7163,16 @@ rs6000_expand_vector_set_var_p8 (rtx target, rtx val, rtx idx)
/* mtvsrd[wz] f0,tmp_val. */
rtx tmp_val = gen_reg_rtx (SImode);
if (inner_mode == E_SFmode)
- emit_insn (gen_movsi_from_sf (tmp_val, val));
+ if (TARGET_DIRECT_MOVE_64BIT)
+ emit_insn (gen_movsi_from_sf (tmp_val, val));
+ else
+ {
+ rtx stack = rs6000_allocate_stack_temp (SFmode, false, true);
+ emit_insn (gen_movsf_hardfloat (stack, val));
+ rtx stack2 = copy_rtx (stack);
+ PUT_MODE (stack2, SImode);
+ emit_move_insn (tmp_val, stack2);
+ }
else
tmp_val = force_reg (SImode, val);
@@ -7143,7 +7196,7 @@ rs6000_expand_vector_set_var_p8 (rtx target, rtx val, rtx idx)
/* lvsl 13,0,idx. */
rtx pcv = gen_reg_rtx (V16QImode);
- emit_insn (gen_altivec_lvsl_reg (pcv, tmp));
+ emit_insn (gen_lvsl (pcv, tmp));
/* vperm 1,1,1,13. */
/* vperm 0,0,0,13. */
@@ -7184,11 +7237,13 @@ rs6000_expand_vector_set (rtx target, rtx val, rtx elt_rtx)
rs6000_expand_vector_set_var_p9 (target, val, elt_rtx);
return;
}
- else if (TARGET_P8_VECTOR && TARGET_DIRECT_MOVE_64BIT)
+ else if (TARGET_VSX)
{
- rs6000_expand_vector_set_var_p8 (target, val, elt_rtx);
+ rs6000_expand_vector_set_var_p7 (target, val, elt_rtx);
return;
}
+ else
+ gcc_assert (CONST_INT_P (elt_rtx));
}
rtx insn = NULL_RTX;
@@ -7218,8 +7273,6 @@ rs6000_expand_vector_set (rtx target, rtx val, rtx elt_rtx)
}
}
- gcc_assert (CONST_INT_P (elt_rtx));
-
/* Simplify setting single element vectors like V1TImode. */
if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode)
&& INTVAL (elt_rtx) == 0)
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index e5191bd1424..3446b03d40d 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -1227,7 +1227,7 @@ (define_expand "vec_init<mode><VEC_base_l>"
(define_expand "vec_set<mode>"
[(match_operand:VEC_E 0 "vlogical_operand")
(match_operand:<VEC_base> 1 "register_operand")
- (match_operand 2 "reg_or_cint_operand")]
+ (match_operand 2 "vec_set_index_operand")]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
rs6000_expand_vector_set (operands[0], operands[1], operands[2]);
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 4404407d330..bcb92be2f5c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5423,7 +5423,7 @@ (define_expand "xl_len_r"
rtx rtx_vtmp = gen_reg_rtx (V16QImode);
rtx tmp = gen_reg_rtx (DImode);
- emit_insn (gen_altivec_lvsl_reg (shift_mask, operands[2]));
+ emit_insn (gen_altivec_lvsl_reg_di (shift_mask, operands[2]));
emit_insn (gen_ashldi3 (tmp, operands[2], GEN_INT (56)));
emit_insn (gen_lxvll (rtx_vtmp, operands[1], tmp));
emit_insn (gen_altivec_vperm_v8hiv16qi (operands[0], rtx_vtmp, rtx_vtmp,
@@ -5507,7 +5507,7 @@ (define_expand "xst_len_r"
rtx rtx_vtmp = gen_reg_rtx (V16QImode);
rtx tmp = gen_reg_rtx (DImode);
- emit_insn (gen_altivec_lvsr_reg (shift_mask, operands[2]));
+ emit_insn (gen_altivec_lvsr_reg_di (shift_mask, operands[2]));
emit_insn (gen_altivec_vperm_v8hiv16qi (rtx_vtmp, operands[0], operands[0],
shift_mask));
emit_insn (gen_ashldi3 (tmp, operands[2], GEN_INT (56)));
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p8.c
index 4149d5240c8..e0c7ee17bde 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p8.c
@@ -58,8 +58,8 @@ vector unsigned char testuu_cst (unsigned char x, vector unsigned char v)
/* { dg-final { scan-assembler-times {\mvperm\M} 12 { target lp64 } } } */
/* -m32 codegen. */
-/* { dg-final { scan-assembler-times {\mstvx\M|\mstxvw4x\M} 4 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mstb\M} 8 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 8 { target { be && ilp32 } } } } */
-/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstvx\M|\mstxvw4x\M} 0 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstb\M} 4 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 4 { target { be && ilp32 } } } } */
+/* { dg-final { scan-assembler-times {\mvperm\M} 12 { target ilp32 } } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p9.c
index b8e751fa2c1..c18444d50b6 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p9.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p9.c
@@ -54,8 +54,8 @@ vector unsigned char testuu_cst (unsigned char x, vector unsigned char v)
/* -m32 codegen. */
/* { dg-final { scan-assembler-times {\mrlwinm\M} 4 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mstb\M} 8 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstb\M} 4 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlxv\M} 8 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlvebx\M} 4 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mxxperm\M} 0 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mxxperm\M} 8 { target ilp32 } } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-double.c
index 1286010bbaf..afd7f7e9924 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-double.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-double.c
@@ -24,15 +24,15 @@ testd_cst (double d, vector double vd)
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 1 { target { ! has_arch_pwr8 } } } } */
-/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 1 { target { ! has_arch_pwr8 } } } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 1 { target { ! has_arch_pwr8 } } } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 1 { target { ! has_arch_pwr7 } } } } */
+/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 1 { target { ! has_arch_pwr7 } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 1 { target { ! has_arch_pwr7 } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 0 { target { has_arch_pwr8 && lp64 } } } } */
-/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 0 { target { has_arch_pwr8 && lp64 } } } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 0 { target { has_arch_pwr7 && lp64 } } } } */
+/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 0 { target { has_arch_pwr7 && lp64 } } } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target { has_arch_pwr8 && lp64 } } } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 1 { target { has_arch_pwr8 && ilp32 } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 1 { target { has_arch_pwr8 && ilp32 } } } } */
-/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 1 { target { has_arch_pwr8 && ilp32 } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target { has_arch_pwr7 && lp64 } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target { has_arch_pwr7 && ilp32 } } } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 0 { target { has_arch_pwr7 && ilp32 } } } } */
+/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 0 { target { has_arch_pwr7 && ilp32 } } } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p8.c
index e458d8f9171..1866ce27176 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p8.c
@@ -29,8 +29,8 @@ testf_cst (float f, vector float vf)
/* { dg-final { scan-assembler-times {\mvperm\M} 3 { target lp64 } } } */
/* -m32 codegen. */
-/* { dg-final { scan-assembler-times {\mstvx\M|\mstxv\M|\mstxvd2x\M} 1 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstvx\M|\mstxv\M|\mstxvd2x\M} 0 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mstfs\M|\mstfsx\M} 2 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mvperm\M} 1 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mvperm\M} 3 { target ilp32 } } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p9.c
index 9684c9f26ba..1c576723146 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p9.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p9.c
@@ -32,4 +32,4 @@ testf_cst (float f, vector float vf)
/* { dg-final { scan-assembler-times {\mlxv\M} 2 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlvewx\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mvperm\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mxxperm\M} 0 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mxxperm\M} 2 { target ilp32 } } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p8.c
index d5fa422c9c1..bcee9b2989e 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p8.c
@@ -57,7 +57,7 @@ testui2_cst(unsigned int x, vector unsigned int v)
/* { dg-final { scan-assembler-times {\mlvewx\M} 4 { target lp64 } } } */
/* { dg-final { scan-assembler-times {\mvperm\M} 12 { target lp64 } } } */
-/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mstvx\M|\mstwx\M|\mstw\M|\mstxvw4x\M} 12 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 8 { target { be && ilp32 } } } } */
+/* { dg-final { scan-assembler-times {\mvperm\M} 12 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstvx\M|\mstwx\M|\mstw\M|\mstxvw4x\M} 4 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 4 { target { be && ilp32 } } } } */
/* { dg-final { scan-assembler-times {\mlvewx\M} 4 { target ilp32 } } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p9.c
index 5cd6b3e0148..5512810ee46 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p9.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p9.c
@@ -57,9 +57,9 @@ testui2_cst(unsigned int x, vector unsigned int v)
/* { dg-final { scan-assembler-times {\mmtvsrwz\M} 8 { target lp64 } } } */
/* { dg-final { scan-assembler-times {\mxxinsertw\M} 8 { target lp64 } } } */
-/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 4 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mstw\M} 8 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 0 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstw\M} 4 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlxv\M} 8 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlvewx\M} 4 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mxxperm\M} 0 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mxxperm\M} 8 { target ilp32 } } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-longlong.c
index 0a0ee31a411..8ca4ac72443 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-longlong.c
@@ -65,6 +65,6 @@ testul2_cst(unsigned long long x, vector unsigned long long v)
/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target lp64 } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 4 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mvperm\M} 0 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 4 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 0 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mvperm\M} 8 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 0 { target ilp32 } } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p8.c
index a479d987bf0..0d9d4e78d5f 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p8.c
@@ -56,7 +56,7 @@ testus2_cst(unsigned short x, vector unsigned short v)
/* { dg-final { scan-assembler-times {\mlvehx\M} 4 } } */
/* { dg-final { scan-assembler-times {\mvperm\M} 12 { target lp64 } } } */
-/* { dg-final { scan-assembler-times {\mlhz\M|\mlvx\M|\mlxv\M|\mlxvw4x\M} 8 { target { be && ilp32 } } } } */
-/* { dg-final { scan-assembler-times {\msthx\M|\mstvx\M|\msth\M|\mstxvw4x\M} 12 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mlhz\M|\mlvx\M|\mlxv\M|\mlxvw4x\M} 4 { target { be && ilp32 } } } } */
+/* { dg-final { scan-assembler-times {\msthx\M|\mstvx\M|\msth\M|\mstxvw4x\M} 4 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mvperm\M} 12 { target ilp32 } } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p9.c
index cea7488b3c6..050adb2c49e 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p9.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p9.c
@@ -55,10 +55,10 @@ testus2_cst(unsigned short x, vector unsigned short v)
/* { dg-final { scan-assembler-times {\mlxv\M|\mlvx\M} 0 { target lp64 }} } */
/* -m32 uses sth/lvehx as part of the sequence. */
-/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 4 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\msth\M} 8 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 0 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\msth\M} 4 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlvehx\M} 4 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mxxperm\M} 0 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mxxperm\M} 8 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlxv\M|\mlvx\M} 8 { target ilp32 } } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79251-run.p7.c b/gcc/testsuite/gcc.target/powerpc/pr79251-run.p7.c
new file mode 100644
index 00000000000..5e29b19768d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr79251-run.p7.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vsx_hw } */
+/* { dg-options "-O2 -mvsx -mdejagnu-cpu=power7" } */
+
+#include <stddef.h>
+#include <altivec.h>
+#include "pr79251.h"
+
+int
+main (void)
+{
+ TEST_VEC_INSERT_ALL (run_test)
+ return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79251.p7.c b/gcc/testsuite/gcc.target/powerpc/pr79251.p7.c
new file mode 100644
index 00000000000..25e227a8036
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr79251.p7.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power7 -mvsx" } */
+
+#include <stddef.h>
+#include <altivec.h>
+#include "pr79251.h"
+
+/* { dg-final { scan-assembler-not {\mstxw\M} } } */
+/* { dg-final { scan-assembler-times {\mlvsl\M} 10 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mlvsr\M} 3 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mvperm\M} 20 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mxxpermdi\M} 10 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mxxsel\M} 7 { target lp64 } } } */
+
+/* { dg-final { scan-assembler-times {\mrlwinm\M} 10 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M} 0 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 0 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstb\M|\msth\M|\mstw\M|\mstfs\M|\mstfd\M} 19 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M} 0 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 7 { target ilp32 } } } */
+
+
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79251.p8.c b/gcc/testsuite/gcc.target/powerpc/pr79251.p8.c
index 178e02fc866..4fc3ea06382 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr79251.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr79251.p8.c
@@ -14,9 +14,9 @@
/* { dg-final { scan-assembler-times {\mxxsel\M} 7 { target lp64 } } } */
/* { dg-final { scan-assembler-times {\mrlwinm\M} 10 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mstxvw4x\M} 6 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M} 4 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mstb\M|\msth\M|\mstw\M|\mstfs\M|\mstfd\M} 12 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mlxvw4x\M} 6 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 4 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M} 0 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 0 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstb\M|\msth\M|\mstw\M|\mstfs\M|\mstfd\M} 1 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M} 0 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 7 { target ilp32 } } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79251.p9.c b/gcc/testsuite/gcc.target/powerpc/pr79251.p9.c
index 2ae2da8c72e..9312aa60409 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr79251.p9.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr79251.p9.c
@@ -16,7 +16,7 @@
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 3 { target lp64 } } } */
/* { dg-final { scan-assembler-times {\mrlwinm\M} 10 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mstxv\M} 10 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mstb\M|\msth\M|\mstw\M|\mstfs\M|\mstfd\M} 12 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mlxv\M} 10 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstxv\M} 0 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mstb\M|\msth\M|\mstw\M|\mstfs\M|\mstfd\M} 1 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mlxv\M} 7 { target ilp32 } } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c
index 0780b01ffab..8841660fd03 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c
@@ -191,10 +191,11 @@ vector unsigned __int128 splat_uint128 (unsigned __int128 x) { return vec_splats
*/
/* { dg-final { scan-assembler-times {\mrldic\M} 0 { target { be && ilp32 } } } } */
-/* { dg-final { scan-assembler-times {\mrldic\M} 64 { target { be && lp64 } } } } */
-/* { dg-final { scan-assembler-times {\mrldic\M} 64 { target le } } } */
-/* { dg-final { scan-assembler-times "xxpermdi" 4 { target be } } } */
-/* { dg-final { scan-assembler-times "xxpermdi" 6 { target le } } } */
+/* { dg-final { scan-assembler-times {\mrldic\M} 65 { target { be && lp64 } } } } */
+/* { dg-final { scan-assembler-times {\mrldic\M} 65 { target le } } } */
+/* { dg-final { scan-assembler-times "xxpermdi" 33 { target be } } } */
+/* { dg-final { scan-assembler-times "xxpermdi" 35 { target le } } } */
/* { dg-final { scan-assembler-times "vspltisb" 2 } } */
/* { dg-final { scan-assembler-times "vspltish" 2 } } */
-/* { dg-final { scan-assembler-times "vspltisw" 2 } } */
+/* { dg-final { scan-assembler-times "vspltisw" 2 { target be } } } */
+/* { dg-final { scan-assembler-times "vspltisw" 23 { target le } } } */
--
2.25.1
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