[PATCH] rs6000: Correct Power8 cost of l2 cache size [PR97329]

[David Edelsohn]

On Wed, Mar 24, 2021 at 1:44 AM Xionghu Luo <luoxhu@linux.ibm.com> wrote:
>
> l2 cache size for Power8 is 512kB, correct the copy paste error from Power7.
> Tested no performance change for SPEC2017.
>
> gcc/ChangeLog:
>
> 2021-03-24  Xionghu Luo  <luoxhu@linux.ibm.com>
>
>         * config/rs6000/rs6000.c (struct processor_costs): Change to
>         512.

This ChangeLog entry should state *what* you are changing to 512.

BTW, the Power8 support was added before everything was public, so it
used Power7 as the information that safely could be shared.  The
explanation in the ChangeLog probably should not characterize it as a
"copy paste error".  The value wasn't updated after the initial Power8
support was added.

Okay with that change.

Thanks, David

> ---
>  gcc/config/rs6000/rs6000.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
> index 616dae35bae..34c4edae20e 100644
> --- a/gcc/config/rs6000/rs6000.c
> +++ b/gcc/config/rs6000/rs6000.c
> @@ -1055,7 +1055,7 @@ struct processor_costs power8_cost = {
>    COSTS_N_INSNS (17),  /* ddiv */
>    128,                 /* cache line size */
>    32,                  /* l1 cache */
> -  256,                 /* l2 cache */
> +  512,                 /* l2 cache */
>    12,                  /* prefetch streams */
>    COSTS_N_INSNS (3),   /* SF->DF convert */
>  };
> --
> 2.25.1
>